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Pull requests: YosysHQ/yosys

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Pull requests list

Add aldff splitting to avoid logic data loops
#5570 opened Dec 23, 2025 by likeamahoney Loading…
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
#5564 opened Dec 22, 2025 by rocallahan Loading…
feature breakreduce
#5563 opened Dec 21, 2025 by nataliakokoromyti Loading…
add breaksop feature
#5562 opened Dec 20, 2025 by nataliakokoromyti Loading…
opt_expr: avoid multiple drivers in test
#5561 opened Dec 19, 2025 by widlarizer Loading…
@widlarizer
splitlarge: split wide $add/$sub operators
#5560 opened Dec 19, 2025 by nataliakokoromyti Loading…
add lut2bmux
#5559 opened Dec 19, 2025 by nataliakokoromyti Loading…
lut2mux: add -word option
#5557 opened Dec 19, 2025 by nataliakokoromyti Loading…
2
Defer redirecting cell outputs when merging cells in opt_merge untill after we've done a full pass over the cells.
#5555 opened Dec 19, 2025 by rocallahan Loading…
@widlarizer
abc: add -word mode which uses word-level cells where possible
#5554 opened Dec 18, 2025 by nataliakokoromyti Loading…
opt_dff: skip convertion to dffe for keep wires
#5548 opened Dec 15, 2025 by phsauter • Draft
4
Document nesting packages as unsupported
#5546 opened Dec 15, 2025 by KrystalDelusion Loading…
Improve error handling in sim
#5544 opened Dec 14, 2025 by KrystalDelusion Loading…
1
@widlarizer
docs: shuffle and expand contributing info documentation
#5531 opened Dec 3, 2025 by widlarizer • Draft
1
Parallelize opt_merge
#5530 opened Dec 3, 2025 by rocallahan Loading…
@widlarizer
8
Makefile: install frontends/verilog/verilog_location.h. discuss needs further discussion on the YosysHQ discourse (https://yosyshq.discourse.group)
#5529 opened Dec 2, 2025 by Muxianesty Loading…
@widlarizer
3
Document and regression-test staged/cosimulation-based verification
#5528 opened Dec 2, 2025 by gussmith23 • Draft
1 task
.github: trigger everything that triggers on main or PRs on merge queue
#5521 opened Nov 27, 2025 by widlarizer Loading…
@widlarizer
2
celltypes: compile-time lookup tables for internal cells
#5512 opened Nov 25, 2025 by widlarizer • Draft
1 task
1
@widlarizer
9
Use digit separators for large decimal integers
#5502 opened Nov 24, 2025 by widlarizer Loading…
@widlarizer
2
Add parsing of verilog module port renaming (aliases)
#5478 opened Nov 10, 2025 by xiota Loading…
2
@widlarizer
proc_mux: use assignment action locations for mux src
#5456 opened Nov 2, 2025 by widlarizer Loading…
2 of 3 tasks
@widlarizer
7
gowin: dsp: Add basic DSP block inferencing for various MULT cells
#5411 opened Oct 7, 2025 by plaes Loading…
@Ravenslofty
3
Unify handling of quoted strings in pass args
#5385 opened Sep 24, 2025 by KrystalDelusion • Draft
4 tasks done
1
@KrystalDelusion
extract_fa: Add parallel processing of partitions
#5373 opened Sep 22, 2025 by jbylicki Loading…
@jix
3
ProTip! Exclude everything labeled bug with -label:bug.