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Hi,
I've found an issue where you get the "Found no match for operator" error if you have logical operations on arrays.
This sould be valid code in VHDL.
Code example:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity foo is end entity foo; architecture rtl of foo is type t_bool_array is array (natural range <>) of boolean; signal result : t_bool_array(3 downto 0); signal a_array : t_bool_array(3 downto 0); signal b_array : t_bool_array(3 downto 0); begin result <= a_array or b_array; result <= a_array and b_array; end architecture;Metadata
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