This repository consolidates three Verilog-based RTL projects into a unified workspace for digital system design:
- Combinational Circuits (
Combinational_Circuits_RTL) - Sequential Circuits (
Sequential_Circuits_RTL) - Finite State Machine (FSM) Designs (
FSM_RTL_Design)
- ADDER-SUBTRACTORS
- ALU
- BASIC GATES
- BCD ADDER
- BCD SUBTRACTOR
- BCD TO 7 SEGMENT DECODER
- BCD TO DECIMAL DECODER
- BCD TO EXCESS-3 CODE CONVERTOR
- CARRY LOOK AHEAD ADDER
- DECIMAL TO BCD ENCODER
- DECODER
- ENCODER
- FULL ADDER
- HALF ADDER
- MAGNITUDE COMPARATOR
- MULTIPLIER
- MUX 16-to-1
- MUX 2-to-1
- MUX 4 to 1
- N-bit ADDER
- ODD-EVEN PARITY GENERATOR
- PRIORITY ENCODER
- RIPPLE CARRY ADDER
- SUBTRACTORS