Extending veriloggen package for VerilogA would make my life and many other electronics enthusiasts easier.

Below I attach argumentation for rising this issue.

Verilog-A Adaptation for Python Libraries

None of the mentioned libraries natively support Verilog-A, as they focus on Verilog HDL (digital circuit description). However, the easiest to adapt for Verilog-A would be:

1. Veriloggen (Most Flexible Option)

• It allows building code structurally, which can make it easier to generate Verilog-A syntax.
• It is designed for Verilog generation, but its generators can be modified to emit analog Verilog-A code.

Possible Adaptation Approach

• Instead of always and assign, you can introduce analog blocks (analog begin ... end).
• Parameters can be easily added (parameter real X = Y;).
• You can create custom functions to describe analog models.

Example Using Veriloggen (Currently Verilog, but Can Be Adapted to Verilog-A)

import veriloggen as vg def generate_verilog_a(): m = vg.Module("MyAmplifier") # Model parameters gain = m.Parameter("gain", 10.0) # Ports vin = m.Input("vin") vout = m.Output("vout") # Here, we would need to add support for `analog begin ... end` body = "V(vout) <+ gain * V(vin);" # Generate code return m.to_verilog() print(generate_verilog_a())

The Easiest Option

Adapting Veriloggen seems the most practical choice because it is based on text-based code generation, making it relatively easy to extend for Verilog-A.