.srcSubpass = VK_SUBPASS_EXTERNAL; .dstSubpass = 0; .srcStageMask = VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; .srcAccessMask = 0; .dstStageMask = VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; .dstAccessMask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT; 

The tutorial claims that: The [depth stencil] reading happens in the VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT stage and the writing in the VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT.

My question is: What happens to the writes in the late frag test, from the earlier subpass, which can here happen after the depth attachment layout transition? Aren't we potentially clearing/transitioning the depth attachment before the previous pass is done writing to it? Couldn't the previous writes corrupt the depth image after we cleared it in this render pass?

Shouldn't the srcMask be late_frag_test?