diff options
author | Jeff Lane <jeffrey.lane@canonical.com> | 2015-12-11 10:41:22 -0500 |
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committer | Jeff Lane <jeffrey.lane@canonical.com> | 2015-12-11 10:41:22 -0500 |
commit | c54e70843f8f06aaba5988bc865157a5673f57b1 (patch) | |
tree | 89b8c5c88ff7ed421ed1ecb517c646471ad578c1 /bin | |
parent | 395a718f8e8a143c14d1c046b7a212432503c934 (diff) |
bin/memory_compare: Added regex matching to lshw class to fix bug where script fails on ARM64 systems
Diffstat (limited to 'bin')
-rwxr-xr-x | bin/memory_compare | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/bin/memory_compare b/bin/memory_compare index 12a14ec..ec307fe 100755 --- a/bin/memory_compare +++ b/bin/memory_compare @@ -24,6 +24,7 @@ import os import sys +import re from math import log, copysign from subprocess import check_output, PIPE @@ -36,10 +37,18 @@ class LshwJsonResult: memory_reported = 0 banks_reported = 0 + + # jlane LP:1525009 + # some systems ID as "memory" and some as "memory:X" + id_regex = re.compile('memory:?\d?') + # Discovered the case can change, my x86 systems used "System Memory" + # Failing ARM system used "System memory" + desc_regex = re.compile('System Memory', re.IGNORECASE) def addHardware(self, hardware): - if hardware['id'] == 'memory': - self.memory_reported += int(hardware.get('size', 0)) + if self.id_regex.match(hardware['id']): + if self.desc_regex.match(hardware.get('description',0)): + self.memory_reported += int(hardware.get('size', 0)) elif 'bank' in hardware['id']: self.banks_reported += int(hardware.get('size', 0)) |