Repository for project work for the course CS220: Computer Organisation.
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Sep 29, 2025 - Tcl
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single-cycle-mips-processor
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Building a Single-Cycle Processor Using MIPS Architecture (VHDL & Xilinx ISE)
vhdl xilinx mips-architecture xilinx-ise mips-processor xilinx-vivado single-cycle-processor single-cycle-mips-processor
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Oct 1, 2024 - VHDL
Designed the ISA for RISC based pipelined 32-bit MIPS processor and implemented a subset of instructions to verify the functionality. Tested the operation using 3 testcases and observed the dataflow between stages.
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Aug 30, 2025 - Verilog
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