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ekb0412/README.md

Hi 👋, I'm Ekansh Bansal

I am a Very Ambitious person🥸

I take up all Learning opportunities to enhance my skills🧾 and know-how to cope up with failures💪

ekb0412

ekb0412


Connect with me:

ekansh-bansal ekanshban483@gmail.com ekanshban483


  • 🔭 I’m currently working as Design Engineer @ Truechip
  • 👯 I’m looking to collaborate on ASIC_VLSI_Projects

Languages and Tools:

c python Verilog System Verilog UVM xilinx Questasim canva


ekb0412 ekb0412

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  1. 100DaysofRTL 100DaysofRTL Public

    "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

    Verilog 103 16

  2. Bridging-AHB-Lite-and-SPI-for-seamless-SoC-communication Bridging-AHB-Lite-and-SPI-for-seamless-SoC-communication Public

    Design & Verification of an efficient AHB Lite to SPI bridge that ensures seamless communication between high-speed AHB-based systems and SPI peripherals, focusing on protocol conversion, data inte…

    Verilog 5 3

  3. UART-Serial-Port-Module-Design-Main-ASIC- UART-Serial-Port-Module-Design-Main-ASIC- Public

    This repository contains a project on a VLSI Front-End design (UART) using Verilog HDL

    Verilog 1