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1. icdk icdk Public

   uvm framework generator

   SystemVerilog 10 1

2. pycde_example pycde_example Public

   A collection of examples showcasing PyCDE and Mini RISC-V implementation.

   Python 9

3. llvm/circt llvm/circt Public

   Circuit IR Compilers and Tools

   C++ 2k 403

4. uvm_bridge uvm_bridge Public

   Bridge systemverilog UVM API with Python by DPI-C, so that Python can be used to write testcases to avoid frequent compilation

   C 5

5. uvm_syoscb uvm_syoscb Public

   A better UVM scoreboard framework, focusing on scalability, architectural separation and connectivity to foreign environments

   SystemVerilog 7 1

6. formal formal Public

   Python 4