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@hellerbarde
Forked from jboner/latency.txt
Created May 31, 2012 13:16
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Latency numbers every programmer should know

Latency numbers every programmer should know

L1 cache reference ......................... 0.5 ns Branch mispredict ............................ 5 ns L2 cache reference ........................... 7 ns Mutex lock/unlock ........................... 25 ns Main memory reference ...................... 100 ns Compress 1K bytes with Zippy ............. 3,000 ns = 3 µs Send 2K bytes over 1 Gbps network ....... 20,000 ns = 20 µs SSD random read ........................ 150,000 ns = 150 µs Read 1 MB sequentially from memory ..... 250,000 ns = 250 µs Round trip within same datacenter ...... 500,000 ns = 0.5 ms Read 1 MB sequentially from SSD* ..... 1,000,000 ns = 1 ms Disk seek ........................... 10,000,000 ns = 10 ms Read 1 MB sequentially from disk .... 20,000,000 ns = 20 ms Send packet CA->Netherlands->CA .... 150,000,000 ns = 150 ms 

Assuming ~1GB/sec SSD

Visual representation of latencies

Visual chart provided by ayshen

Data by Jeff Dean

Originally by Peter Norvig

Lets multiply all these durations by a billion:

Magnitudes:

Minute:

L1 cache reference 0.5 s One heart beat (0.5 s) Branch mispredict 5 s Yawn L2 cache reference 7 s Long yawn Mutex lock/unlock 25 s Making a coffee 

Hour:

Main memory reference 100 s Brushing your teeth Compress 1K bytes with Zippy 50 min One episode of a TV show (including ad breaks) 

Day:

Send 2K bytes over 1 Gbps network 5.5 hr From lunch to end of work day 

Week

SSD random read 1.7 days A normal weekend Read 1 MB sequentially from memory 2.9 days A long weekend Round trip within same datacenter 5.8 days A medium vacation Read 1 MB sequentially from SSD 11.6 days Waiting for almost 2 weeks for a delivery 

Year

Disk seek 16.5 weeks A semester in university Read 1 MB sequentially from disk 7.8 months Almost producing a new human being The above 2 together 1 year 

Decade

Send packet CA->Netherlands->CA 4.8 years Average time it takes to complete a bachelor's degree 
@eduard93
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eduard93 commented Jan 3, 2022

What about register access timings?

@hellerbarde
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hellerbarde commented Jan 6, 2022

@eduard93 I think register access happens within one CPU cycle. Which, at 2.4 GHz would be 0.417 nanoseconds, which is very similar to the L1 cache reference. I'm not sure if that's true, because I'm not incredibly familiar with modern CPUs. Feel free to fact check this.

@Yougigun
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Yougigun commented Nov 7, 2022

thasnk

@zhangchiisgy
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nice

@sitansu04
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thats cool!

@weizhiwen
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cool!

@Shivam5022
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thanks for this, loved it

@KimJin788
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Cool

The human reaction time:
Average Reaction Times

  • Visual stimulus: 150-300ms
  • Audio stimulus: 140-160ms
  • Touch stimulus: 130-150ms
@popatrader
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Here's a nanosecond: https://www.youtube.com/watch?v=9eyFDBPk4Yw

That's really amazing way to see

@C-Jeril
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C-Jeril commented Nov 9, 2025

You might find some reaction games here: https://kuakua.app/games/reaction-speed

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