Add basic support for Microchip PIC32CX SG Family devices

boards/microchip/pic32c/pic32cx_sg61_cult/Kconfig.pic32cx_sg61_cult

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+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PIC32CX_SG61_CULT
+select SOC_PIC32CX1025SG61128

boards/microchip/pic32c/pic32cx_sg61_cult/board.cmake

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+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=PIC32CX1025SG61128" "--speed=4000")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/microchip/pic32c/pic32cx_sg61_cult/board.yml

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+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+ name: pic32cx_sg61_cult
+ full_name: PIC32CX SG61 Curiosity Ultra
+ vendor: microchip
+ socs:
+ - name: pic32cx1025sg61128

boards/microchip/pic32c/pic32cx_sg61_cult/doc/index.rst

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+.. zephyr:board:: pic32cx_sg61_cult
+
+Overview
+********
+
+The PIC32CX SG61 Curiosity Ultra evaluation kit is a hardware platform
+to evaluate the Microchip PIC32CX SG60/SG61 microcontrollers, and the
+evaluation kit part number is EV09H35A. The evaluation kit offers a
+set of features that enables the PIC32CX SG60/SG61 users to get started with
+the PIC32CX SG60/SG61 peripherals, and to obtain an understanding of how to
+integrate the device in their own design.
+
+Hardware
+********
+
+- 128-pin TQFP PIC32CX SG61 microcontroller
+- 32.768 kHz crystal oscillator
+- 12 MHz crystal oscillator
+- 1024 KiB flash memory and 256 KiB of RAM
+- Two yellow user LED
+- One green board power LED
+- One mechanical user push button
+- One reset button
+- USB interface, Host or Device
+- One driven shield Touch button
+- Virtual COM port (CDC)
+- Programming and debugging of on-board PIC32CX SG60/SG61 through Serial Wire Debug (SWD)
+- Arduino uno connector
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The `PIC32CX SG61 Curiosity Ultra User Guide`_ has detailed information about board connections.
+
+Programming & Debugging
+***********************
+
+.. zephyr:board-supported-runners::
+
+Flash Using J-Link
+==================
+
+To flash the board using the J-Link debugger, follow the steps below:
+
+1. Install J-Link Software
+
+ - Download and install the `J-Link software`_ tools from Segger.
+ - Make sure the installed J-Link executables (e.g., ``JLink``, ``JLinkGDBServer``)
+ are available in your system's PATH.
+
+2. Connect the Board
+
+ - Connect the `J32 Debug Probe`_ to the board's **CORTEX DEBUG** header.
+ - Connect the other end of the J32 Debug Probe to your **host machine (PC)** via USB.
+ - Connect the DEBUG USB port on the board to your host machine to **power up the board**.
+
+3. Build the Application
+
+ You can build a sample Zephyr application, such as **Blinky**, using the ``west`` tool.
+ Run the following commands from your Zephyr workspace:
+
+ .. code-block:: console
+
+ west build -b pic32cx_sg61_cult -p -s samples/basic/blinky
+
+ This will build the Blinky application for the ``pic32cx_sg61_cult`` board.
+
+4. Flash the Device
+
+ Once the build completes, flash the firmware using:
+
+ .. code-block:: console
+
+ west flash
+
+ This uses the default ``jlink`` runner to flash the application to the board.
+
+5. Observe the Result
+
+ After flashing, **LED1** on the board should start **blinking**, indicating that the
+ application is running successfully.
+
+References
+**********
+
+PIC32CX SG61 Product Page:
+ https://www.microchip.com/en-us/product/PIC32CX1025SG61128
+
+PIC32CX SG61 Curiosity Ultra evaluation kit Page:
+ https://www.microchip.com/en-us/development-tool/ev09h35a
+
+.. _PIC32CX SG61 Curiosity Ultra User Guide:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/UserGuides/PIC32CX-SG41-SG61-Curiosity-Ultra-User-Guide-DS70005520.pdf
+
+.. _J-Link software:
+ https://www.segger.com/downloads/jlink
+
+.. _J32 Debug Probe:
+ https://www.microchip.com/en-us/development-tool/dv164232

boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.dts

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <microchip/pic32c/pic32cx_sg/pic32cx_sg61/pic32cx1025sg61128.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+model = "PIC32CX SG61 Curiosity Ultra";
+compatible = "pic32cxsg61,cultra", "microchip,pic32cx1025sg61128", "microchip,pic32cx";
+
+chosen {
+zephyr,sram = &sram0;
+zephyr,flash = &flash0;
+};
+
+aliases {
+led0 = &led1;
+sw0 = &button0;
+};
+
+leds {
+compatible = "gpio-leds";
+
+led1: led_1 {
+gpios = <&portc 21 GPIO_ACTIVE_HIGH>;
+label = "Yellow LED";
+};
+
+led2: led_2 {
+gpios = <&porta 16 GPIO_ACTIVE_HIGH>;
+label = "Yellow LED";
+};
+};
+
+buttons {
+compatible = "gpio-keys";
+
+button0: button_0 {
+gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+label = "SW1";
+zephyr,code = <INPUT_KEY_0>;
+};
+};
+};
+
+&flash0 {
+partitions {
+compatible = "fixed-partitions";
+
+#address-cells = <1>;
+#size-cells = <1>;
+
+storage_partition: partition@7c000 {
+label = "storage";
+reg = <0x0007c000 0x4000>;
+};
+};
+};
+
+&cpu0 {
+clock-frequency = <48000000>;
+};
+
+&porta{
+status="okay";
+};
+
+&portb{
+status="okay";
+};
+
+&portc{
+status="okay";
+};

boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult.yaml

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+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: pic32cx_sg61_cult
+name: PIC32CX SG61 Curiosity Ultra
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+flash: 1024
+ram: 256
+supported:
+ - gpio
+vendor: microchip

boards/microchip/pic32c/pic32cx_sg61_cult/pic32cx_sg61_cult_defconfig

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+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_ARM_MPU=y

dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+
+cpu0: cpu@0 {
+device_type = "cpu";
+compatible = "arm,cortex-m4f";
+reg = <0>;
+#address-cells = <1>;
+#size-cells = <1>;
+
+mpu: mpu@e000ed90 {
+compatible = "arm,armv7m-mpu";
+reg = <0xe000ed90 0x2c>;
+};
+};
+};
+
+soc {
+flash0: flash@0 {
+compatible = "soc-nv-flash";
+write-block-size = <8>;
+reg = <0x0 DT_SIZE_K(1024)>;
+};
+
+sram0: memory@20000000 {
+compatible = "mmio-sram";
+reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+porta: gpio@41008000 {
+status = "disabled";
+compatible = "microchip,port-g1-gpio";
+reg = <0x41008000 0x80>;
+gpio-controller;
+#gpio-cells = <2>;
+#microchip,pin-cells = <2>;
+};
+
+portb: gpio@41008080 {
+status = "disabled";
+compatible = "microchip,port-g1-gpio";
+reg = <0x41008080 0x80>;
+gpio-controller;
+#gpio-cells = <2>;
+#microchip,pin-cells = <2>;
+};
+};
+};
+
+&nvic {
+arm,num-irq-priority-bits = <3>;
+};

dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_100.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Device-tree nodes specific to 100-pin package variants */
+
+#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>
+
+/ {
+soc {
+portc: gpio@41008100 {
+status = "disabled";
+compatible = "microchip,port-g1-gpio";
+reg = <0x41008100 0x80>;
+gpio-controller;
+#gpio-cells = <2>;
+#microchip,pin-cells = <2>;
+};
+};
+};

dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_128.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Device-tree nodes specific to 128-pin package variants */
+
+#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>
+
+/ {
+soc {
+portc: gpio@41008100 {
+status = "disabled";
+compatible = "microchip,port-g1-gpio";
+reg = <0x41008100 0x80>;
+gpio-controller;
+#gpio-cells = <2>;
+#microchip,pin-cells = <2>;
+};
+
+portd: gpio@41008180 {
+status = "disabled";
+compatible = "microchip,port-g1-gpio";
+reg = <0x41008180 0x80>;
+gpio-controller;
+#gpio-cells = <2>;
+#microchip,pin-cells = <2>;
+};
+};
+};

dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_64.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Device-tree nodes specific to 64-pin package variants */
+
+#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>

dts/arm/microchip/pic32c/pic32cx_sg/common/pic32cx_sg_80.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Device-tree nodes specific to 80-pin package variants */
+
+#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg.dtsi>
+
+/ {
+soc {
+portc: gpio@41008100 {
+status = "disabled";
+compatible = "microchip,port-g1-gpio";
+reg = <0x41008100 0x80>;
+gpio-controller;
+#gpio-cells = <2>;
+#microchip,pin-cells = <2>;
+};
+};
+};

dts/arm/microchip/pic32c/pic32cx_sg/pic32cx_sg41/pic32cx1025sg41064.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg_64.dtsi>

dts/arm/microchip/pic32c/pic32cx_sg/pic32cx_sg41/pic32cx1025sg41080.dtsi

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+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <microchip/pic32c/pic32cx_sg/common/pic32cx_sg_80.dtsi>