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verilator

Here are 18 public repositories matching this topic...

olofk / edalize

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

Updated Oct 15, 2025
Python

dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

poucotm / SublimeLinter-contrib-verilator

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

linter sublime-text sublimelinter linter-plugin verilog verilator

Updated Jun 26, 2024
Python

verilator / verilator_ext_tests

Extended and external tests for Verilator testing

Updated Sep 17, 2025
Python

meiniKi / SimIO

SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

simulation verilog systemverilog testbench digital-design verilator

Updated Sep 2, 2024
Python

esynr3z / playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

eda verilog vcs systemverilog icarus-verilog hdl modelsim verilator

Updated Dec 25, 2022
Python

dau-dev / verilator-python

Python/PyPI wrapper for Verilator

hardware verilog systemverilog verilator

Updated Oct 12, 2025
Python

ECE320 / riscv-tester

Tests your ECE 320 Single Cycle RISC-V Processor: Up to PD5

python python3 verilog hdl verilog-hdl risc-v verilator riscv32i

Updated Dec 2, 2022
Python

npatsiatzis / fifo_asynchronous

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 8, 2023
Python

npatsiatzis / cdc_handshake

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 9, 2023
Python

npatsiatzis / fir

vhdl systemverilog verilator cocotb sby pyuvm

Updated Oct 8, 2023
Python

npatsiatzis / moving_average

vhdl systemverilog verilator cocotb pyuvm

Updated Oct 8, 2023
Python

bjohnsonfl / aes

Python AES

python cryptography encryption aes vhdl pytest systemverilog decryption hdl testbench block-cipher verilator cocotb cosimulation aes256-cbc

Updated Jun 1, 2025
Python

npatsiatzis / recirculation_mux

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 9, 2023
Python

npatsiatzis / fizzbuzz

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 7, 2023
Python

npatsiatzis / simple_adder

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 6, 2023
Python

TatsuProject / chipforge_eda_server

EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

eda verilog systemverilog verilator bittensor chipforge

Updated Oct 20, 2025
Python

NCKU-AISLAB / force-ai

FORCE AI: Fast Optimization for Resource-Constrained Efficient AI Inference

tutorials cnn verilator ai-compiler ai-accelerator

Updated Jun 20, 2025
Python

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