1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage fo
A 16 bit Five Stage Pipelined MIPS Processor Verification using UVM
Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.
Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.
Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).
Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.
SystemVerilog tutorial on how and why to use clocking blocks
This repository as collection of unique & some very important verilog system verilog code that i have worked on. Hope it helps.
verification of apb and ahb bridge using UVNIVERSAL VERIFICATION METHODOLOGY
Emulation, implementation and verification of RISC-V core with I,M and Zbb extensions
Add a description, image, and links to the uvm-verification topic page so that developers can more easily learn about it.
To associate your repository with the uvm-verification topic, visit your repo's landing page and select "manage topics."