A Single Cycle Risc-V 32 bit CPU
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Oct 3, 2025 - SystemVerilog
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single-cycle-processor
Here are 73 public repositories matching this topic...
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor
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Dec 7, 2024 - Verilog
LEGv8 CPU implementation and some tools like a LEGv8 assembler
awk verilog pipeline-processor pipeline-cpu single-cycle hennessy patterson legv8-arm legv8 single-cycle-processor hennessy-and-patterson
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Nov 28, 2020 - Verilog
Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA
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Apr 23, 2023 - SystemVerilog
Single Cycle 32 bit MIPS
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Dec 24, 2022 - SystemVerilog
Single Cycle CPU using the RV32I Base Instruction set
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Jul 15, 2023 - Verilog
21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.
cpu virtual-memory tlb risc-v cpu-emulator computer-organization tlb-simulator riscv64 computer-organisation-architechure risc-v-assembly single-cycle-processor 5-stage-pipeline computer-organization-lab computer-organization-and-design
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Apr 11, 2023 - Verilog
Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).
fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
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Jul 21, 2025 - SystemVerilog
A RISC-V Single Cycle Processor which is done in verilog.
module verilog vivado computer-architecture risc-v 32-bit hardware-description-language riscv32 risc-architecture-processor single-cycle-processor testbench-generator-verilog
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Jul 20, 2020 - Verilog
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
mips mips-architecture mips-simulator pipelined-processors single-cycle-processor multi-cycle-processor
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Aug 31, 2020 - SystemVerilog
Aleph is a single cycle processor that carries out one instruction in a single clock cycle
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Aug 8, 2023 - Scala
Single and Multi-cycle ARM processors implemented using VHDL
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Jan 26, 2021 - VHDL
This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.
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Aug 14, 2023 - Verilog
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board
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Dec 7, 2022 - Tcl
This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".
vhdl verilog microprocessor hardware-designs computer-architecture pipeline-processor rv32i single-cycle-processor 5-stage-pipeline 3-stagepipeline fetch-stage-pipeline
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May 24, 2024 - Verilog
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.
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Feb 19, 2022 - Verilog
Main website of the HW Lab guide by NITC
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Aug 23, 2024
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
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May 12, 2024 - SystemVerilog
RISC-V 32IM - Dobby SOC
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Jul 1, 2022 - Verilog
This rep contains neighbour's cpu. Single-cycle/Multi-cycle CPU implementation in vhdl using ISE Xiling for the course 'Computer Organization' at TUC
vhdl mips-assembly xilinx-ise single-cycle-processor multi-cycle-processor computer-organization-and-design
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Jul 29, 2024 - VHDL
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