Uploaded byGaurav Verma
ARM CORTEX M3 PPT
The document provides an overview of the ARM Cortex processor, highlighting its performance efficiency, low power consumption, and ease of use for 32-bit applications. It details the features of the Cortex M3 core, including its Harvard architecture, CPU registers, and the Nested Vectored Interrupt Controller (NVIC) for efficient interrupt handling. Additionally, it discusses memory management and various operational modes, emphasizing the benefits for both developers and end-users.
ARM CORTEX M3 PPT
- 1. ARM CORTEX PROCESSOR GauravVerma A i P fAssistant Professor Department of Electronics and Communication Engineering Jaypee Institute of Information and TechnologyJ yp gy Sector-62, Noida, Uttar Pradesh, India. il @jii i ii k @ il 1 Email: gaurav.verma@jiit.ac.in, gaurav.iitkg@gmail.com
- 2. WHY CORTEX? G tf ffi i ll i k t b d ith tGreater performance efficiency: allowing more work to be done without increasing the frequency or power requirements. Low power consumption: enabling longer battery life, especially criticalLow power consumption: enabling longer battery life, especially critical in portable products including wireless networking applications. Enhanced determinism: guaranteeing that critical tasks and interruptsg g p are serviced as quickly as possible and in a known number of cycles. Ease of use: providing easier programmability and debugging for the b f b d b bgrowing number of 8-bit and 16-bit users migrating to 32 bits. Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8 bit and 16 bit devices and enabling low end 32 bitof legacy 8-bit and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less than US$1 for the first time. Wide choice of development tools: from low-cost or free compilers to 2 f p p full-featured development suites from many development tool vendors
- 3. My Processor belongsto which architecturearchitecture 3
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- 5. Processor vs MCU Focustodayy 5
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- 8. Features of ARMCORTEX M3 Processor Harvard bus architectureHarvard bus architecture –3-stage pipeline with branch speculation Configurable nested vectored interrupt controller (NVIC) Wake-up Interrupt Controller (WIC) –Enables ultra low-power standby operation Extended configurability of debug and trace capabilitiesg y g p –More flexibility for meeting specific market requirements Optional components for specific market reqs. M P t ti U it (MPU)–Memory Protection Unit (MPU) –EmbeddedTrace Macrocell™(ETM™) Support for fault robust implementations via configurable observation interface –EC61508 standard SIL3 certification Physical IP support 8 y pp –Power Management Kit™(PMK) + low-power standard cell libraries and memories enable0.18μm Ultra-Low Leakage (ULL) process
- 9. ARM Cortex Pipeline Hd h S I D b blHarvard architecture- Separate Instruction & Data buses, enable parallel fetch & store, Advanced 3-Stage Pipeline Includes Branch Forwarding & Speculation,AdditionalWrite-Back via Bus Matrix.Forwarding & Speculation,AdditionalWrite Back via Bus Matrix. 9
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- 11. CPU Registers • Thereare 16 registers, which are of 32 bit wide. • Register R0-R12 are general purpose registers. • Register R13 is used as the stack pointer• Register R13 is used as the stack pointer. • There are two stacks i.e. main stack and process stack depends upon in which mode the processor is working. • R14 is the link register, which is used to store the return address of procedure call. For nested calls the compiler will automatically store the R14 on the stack. • R15 is the normal program counter. 11
- 12. Program Status Register:XPSR 12
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- 29. Accessing of BitBand & Alias Regiong g 29
- 30. Read ModifyWriteVs BitBandingy g 30
- 31. SystemTimer (SysTick)Syste e(Sys c ) 31
- 32. SysTick Control &Status Registery g 32
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- 35. ARM7 vs ARMCORTEX INTERRUPTARM7 vs ARM CORTEX INTERRUPT HANDLING 35
- 36. Features Description ofNVIC N d V d I C ll (NVIC) d h hNested Vectored Interrupt Controller (NVIC) integrated with the processor for low latency Configurable number 1 to 240 of external interrupts–Configurable number, 1 to 240, of external interrupts –Configurable number, 3 to 8, of bits of priority. –Dynamic reprioritization of interruptsDynamic reprioritization of interrupts. –Priority grouping. This allows selection of pre-empting interrupt levels and non pre-empting interrupt levelsp p p g p –Support for tail-chaining, and late arrival, of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts –Processor state automatically saved on interrupt entry, and restored on interrupt exit with no instruction overhead 36 restored on interrupt exit, with no instruction overhead.
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- 38. NVIC Operation ExceptionEntry & Exitp p y 38
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- 43. NVIC Configuration &Use 43
- 44. NVIC Configuration &Use 44
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- 47. System Handler PriorityRegister 1 47
- 48. System Handler PriorityRegister 2 System Handler Priority Register 3 48
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- 50. Interrupt Set EnableRegisters 50
- 51. Interrupt Clear EnableRegisters 51
- 52. Interrupt Set PendingRegisters 52
- 53. Interrupt Clear PendingRegisters 53
- 54. Interrupt Active BitRegisters 54
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- 57. Application Interrupt andReset Control Register 57
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- 62. Level Sensitive andPulse Interrupts 62
- 63. Hardware & SoftwareControl 63
- 64. Hardware & SoftwareControl 64
- 65. Entering Low PowerModes 65
- 66. Entering Low PowerModes 66