Faculty Orientation Workshop

On
BE(E & TC)Revised 2019 Course

Subject: VLSI Design & Technology

B.E E & TC
Under the aegis of
Board of Studies
(Electronics & Telecommunication Engineering)
Savitribai Phule Pune University, Pune
[14-16 July 2022]

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Unit 6:- VLSI Testing and Analysis

• Types of Faults
• Need of Design for Testability (DFT)
• DFT Guidelines
• Testability
• Fault Models
• Path Sensitizing
• Test pattern generation
• Sequential Circuit Test
• Build In Self Test (BIST)
• JTAG & Boundary Scan
• TAP Controller

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Course Objectives and Course outcomes

Course Objective:
To realize importance of testability in logic circuit design.
Course Outcome:
Apply knowledge of testability in design and Build In Self
Test (BIST)circuit
PO covered :
PO1 :Engineering knowledge: Apply the knowledge of
engineering fundamentals, and an engineering
specialization to the solution of complex engineering
problems.
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VERIFICATION
AND
MANUFACTURING TEST

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Test your knowledge

Circuit nodes cannot be probed for monitoring or

excitation without testability.
a) true
b) false

The entire surface of the chip other than the pads are sealed by an overglass
layers
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NEED FOR TESTING

Wafer consist of number of dies

Due to the complexity of

manufacturing process, Small
imperfection in starting material
may occurs.

Operating frequencies have increased from 100KHz to

several GHz
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NEED FOR TESTING
Decreasing feature size increases probability of
defects during manufacturing process.

– A single faulty transistor or wire results in faulty

IC

– Testing required to guarantee

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TESTING

 Most expensive process of chips:

–Logic verification accounts for > 50% of design
effort for many chips
–Debug time after fabrication is large
–Shipping defective parts can sink a company

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TESTING

Example: Intel FDIV bug

– Intel introduced the Pentium line of processors in
March 1993.

– Logic error not caught until > 1M units shipped

– Recall cost $450M (!!!)

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It is the aim of test procedure to determine which die
are good and should be used in end system.
• Testing of die can occur at
The wafer level
Packaged chip level
Board level
System level
In the field

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• Test may be categorized in to two main parts

1)Functionality test
2)Manufacturing test

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Functionality test
• It checks the functionality of the circuit
• Check the correctness of the layout
• It is traditional method

Does this adder adds?

Does this counter counts?
Does this state machine yields the right o/ps at the
right clock cycle?

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It Includes

• Functional simulation ( gate level)

• DRC (Design Rule Checking),
• circuit extraction (LVS)
• performance verification and reliability verification (timing
analysis)

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Manufacturing test

• It verify the each function of chip

• Used to verify that every gate operates as expected

• Defect that can be eliminate using manufacturing tests

are
• Layer to layer short ( metal to metal)
• Discontinuous wire
• Thin oxide shorts to substrate or well
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Defect that can be eliminate using manufacturing tests are

• Node shorted to power or ground

• Node shorted to each other
• Input floating
• Output disconnected
• Checking the noise margin
• Speed test

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Manufacturing Test

– Must test chips after manufacturing before delivery to

customers to only ship good parts

• Manufacturing testers are very expensive

– Careful selection of test vectors can
Minimize time on tester

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Fault models

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Types of faults

• A model for how fault occur and their impact on circuit is

called a fault model. A fault model for every circuit is proposed
before actual testing.
• Two popular fault models are
• 1)Stuck at fault
• 2)Stuck-open or stuck –short faults

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Stuck-At Faults

– Usually failures are shorts between two conductors or

opens in a conductor.
– Most of the failures in the circuit is because of nodes
to be “stuck-at” 0 or 1, i.e. shorted to GND or VDD
– Stuck at fault model assigns a fixed value(0/1)to signal
line in the circuit, which is an input or output of
gate/flip flop.

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Stuck-open and stuck-short

– Stuck-open and stuck short faults are usually referred

as transistor faults. Physical faults which occurs at
manufacturing level are called as defects. The
electrical or logical level faults by physical defects are
referred as defect oriented faults such as open links,
improper semiconductor doping, bridging faults.

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Open circuit

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Fault simulation

Test vector is [1 1]
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Testing AND Gates for Stuck-At Faults

Stuck-At Faults 0 Stuck-At Faults 1

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Testing OR Gates for Stuck-At Faults

Stuck-At Faults 1 Stuck-At Faults 0

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Example

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Input Fault
W1 w2 w3 a\0 a\1 b\0 b\1 c\0 c\1 d\0 d\1 f\0 f\1
0 0 0 √ √ √
0 0 1 √ √ √ √
0 1 0 √ √ √ √
0 1 1 √ √ √ √
1 0 0 √ √
1 0 1 √ √
1 1 0 √ √
1
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1 1 VLSI Design & Technology
√
Test set = {001, 010, 011, 100}

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• Transition Fault (TF)
– A cell or a line that fails to undergo a 0=>1 or a 1=>0
transition

• Coupling Fault (CF)

– A write operation to one cell changes the content of a
second cell

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Address Decoder Fault (AF)

–With a certain address , no cell will be accessed.

–A certain cell is never accessed.
–with a certain address ,multiple cells are accessed
simultaneously.
–A certain cell can be accessed by multiple addresses .

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Fault Coverage

• Ideally testing involve detecting all possible faults in a device

under test (DUT). The extent of testing decides the percentage
of faults that can be detected. Detection of all possible faults in
DUT corresponds to 100% test coverage.
• Fault coverage is defined as the percentage of fault that can be
detected by the applied test vector. Fault coverage gives a
measure of goodness of test program. High fault coverage is
desirable during manufacturing test.

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Fault Coverage

• % Fault Coverage=Number of faults detected/Total nodes in the

circuit.

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Path Sensitizing

• Deriving a test set by considering the individual

faults on all wires in a circuit is not attractive from
the practical point of view.
• There are too many wires and too many faults to
consider.

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• A better alternative is to deal with several wires that
form a path as an entity that can be tested for several
faults using a single test.

• It is possible to activate a path so that the changes in the

signal that propagates along the path have a direct
impact on the output signal.

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Technique used in path Sensitizing

• To sensitize a path through an input of an AND or

NAND gate, all other inputs must be set to 1.

• To sensitize a path through an input of an OR or

NOR gate, all other inputs must be 0.

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• Figure illustrates a path from input w1 to output f ,
through three gates, which consists of wires a, b, c,
and f .
• The path is activated by ensuring that other paths in
the circuit do not determine the value of the output f
• Thus the input w2 must be set to 1 so that the signal
at b depends only on the value at a.

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• The input w3 must be 0 so that it does not affect the
NOR gate, and w4 must be 1 to not affect the AND gate.
• if w1 = 0 the output will be f = 1,
• if w1 = 1 the output will be f = 0.
• path is sensitized from w1 to f.

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Effect of faults along a sensitized path

• The fault a/0 in Figure will cause f = 1 even if w1 =

1.
• The same effect occurs if the faults b/0 or c/1 are
present.
• w1w2w3w4 = 1101 detects faults a/0, b/0, and c/1.

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Effect of faults along a sensitized path

• Similarly, if w1 = 0, the output should be f = 1.

• But if any of the faults a/1, b/1, or c/0 is present,

the output will be f = 0.

• Hence these three faults are detectable using the

test 0101.
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Testing Sequential Logic

• Testing sequential logic is generally much

more difficult than testing combinational logic

• large number of test sequences may be

required.

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Brute-force approach
• Schematically enumerating all possible candidates for
the solution and checking whether each candidate
satisfies the problem's statement.

• A large number of tests are required to test exhaustively

all states and all state transitions in the machine

Can we derive a relatively small set of test sequences

that will adequately test the circuit?
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• One way to derive test sequences for a sequential circuit
is to convert it to an iterative circuit.

• The iterative circuit means that the combinational part of

the sequential circuit is repeated several times to indicate
the condition of the combinational part of the circuit at
each time.

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• Since the iterative circuit is a combinational circuit, we
could derive test vectors for the iterative circuit using
one of the standard methods for combinational circuits.

• Figure shows a standard Mealy sequential circuit and the

corresponding iterative circuit.

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• In these figures, X, Z, and Q can either be single
variables or vectors.

• The iterative circuit has k + 1 identical copies of

the combinational network used in the sequential
circuit, where k + 1 is the length of the sequence
used to test the sequential circuit.

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• For the sequential circuit, X(t) represents a
sequence of inputs in time. In the iterative circuit,
X(0) X(1) . . . X(k) represents the same sequence in
space.

• Each cell of the iterative circuit computes Z(t) and

Q(t + 1) in terms of Q(t) and X(t).

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• The leftmost cell computes the values for t = 0,
the next cell for t = 1, and so on.

• After the test vectors have been derived for the

iterative circuit, these vectors become the input
sequences used to test the original sequential
circuit.

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DFT

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• Design for testability shows the fault model to test the chip in manufacturing process.

• DFT techniques are design efforts specifically employed to ensure that a device is testable.

• In general, DFT is achieved by employing extra H/W.

• Need for DFT
During Fabrication process several types of defects may exists such as catastrophic,
crystalline.
Catastrophic defect is due to contamination, resulting in destruction of all transistors on
chip.
And crystalline defect is because of destruction of a single transistor on chip.

• The aspect of testability is based on two key concepts

Controllability and observability
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Observability

• Ease of observing a node by watching external

output pins of the chip

• you should be able to observe directly or with

moderate indirection every gate output within an
integrated circuit.

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Controllability

• Ease of forcing a node to 0 or 1 by driving input

pins of the chip
Example:
• Making all flip-flops resettable via a global reset
signal is one step toward good controllability.

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Design for Test

• Design the chip to increase observability and

controllability

• logic blocks could enter test mode where they

generate test patterns and report the results
automatically.

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What can we do to increase testability

Increase observability

•add more pins (?!)

•add small “probe” bus, selectively
•enable different values onto bus
•cheap read-out of all state information

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What can we do to increase testability

• Increase controllability

• provide easy setup of internal state

• use muxes to isolate sub-modules and
• select sources of test data as inputs

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Scan-based test techniques

• all registers are chained into one huge shift register

which can be loaded/read-out bit serially.

• Observe and control all states

• Requires 3 extra pins and a bit more logic in FFs

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• Circuit is operated in two modes

• Test mode
• Normal mode

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(1)in “test” mode, shift in operation place a new values for all
register bits thus setting up the inputs to the combinational logic
(2) clock the circuit once in “normal” mode, latching the outputs of
the combinational logic back into the registers
(3) in “test” mode, shift out the values of all register bits and
compare against expected results.
One can shift in new test values at the same time (i.e., combine
steps 1 and 3).

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Operation :

• SCAN is asserted and CLK is pulsed eight times

to load the first two ranks of 4-bit registers with
data.

• SCAN is deasserted and CLK is asserted for one

cycle to operate the circuit normally with
predefined inputs.
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• SCAN is then reasserted and CLK asserted eight
times to read the stored data out.

• At the same time, the new register contents can be

shifted in for the next test..

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• In this scheme, every input to the combinational
block can be controlled and every output can be
observed.

• In addition, running a random pattern of l's and

O's through the scan chain can test the chain itself

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Partial scan
• Sometimes it is not efficient to implement scan in
every location where a register is used (signal
processing).
• Only selected blocks are scanned.
• Area reduced and speed increased.
• Sequential Automatic Test Pattern Generator (ATPG)
is used for partial scan.
• In this mode all the flip flops are not into a scan path.
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Full scan
• Full scan provides total controllability and
observability. It provides high fault coverage for
structural defects.
• Combinational Automatic Test Pattern Generator
(ATPG) is used for full scan.

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Boundary Scan

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Boundary Scan
• What is Boundary Scan?
Boundary scan is a methodology allowing complete
controllability and observability of the boundary
pins of a JTAG

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Boundary Scan

• Boundary scan check is a test technique which uses scan

methodology involving shift registers. The shift register
control monitors signal at each input and output pins that
are connected in serial fashion to form a chain of data
register call boundary scan registers.
• It increases fault coverage
• It is time efficient
• It is very simple

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Boundary Scan

• Boundary Scan Standards

Joint Test Action Group
Element Test Maintenance
VHSIC Test and Maintenance
Testability Bus Standard

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Boundary scan test methodology. The boundary scan shift
register prevents output from rippling as data is shifted through
the shift register during scan operation.
The boundary scan path is having serial input output cells/pads
and has appropriate clock pads. PackageInterconnect

CHIP B CHIP C

Serial Data Out

CHIP A CHIP D

IO pad and Boundary Scan

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Serial Data In
JTAG (1149.1 STANDARD)
• IEEE 1149.1, a standard for boundary scan. JTAG is meant
for verifying wheatehr the circuit has been mounted on
circuit board [Link] standar specifies method to
test device functionality and interconnections through Test
Access port (TAP) and boundary scan.
Features:
• Boundary scan testing of IC’s and boards.
• Debug Embedded devices.
• System level debug capability
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• Used for?
• Functional Tests
• Interconnect tests
• Built-in self test procedures.

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JTAG for testing internal circuitry JTAG for testing external circuitry

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JTAG Architecture
The Instruction Register is serially
loaded with the instructions. The
operation to be performed are
selected by these instructions.
User defined data registers are set of
shift registers. Stimuli needed for an
operation are loaded serially into data
registers.
TAP is general purpose port which
provides access to control logic for
operation of JTAG.
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VLSI Design & Technology
Advantages

• The need for physical test points on the board is

eliminated
• Less costly test fixtures.
• Reduced time on in-circuit test systems.
• Increased use of standard interfaces.
• Faster time-to-market.

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Built-In Self-Test

• As digital systems become more and more

complex, they become much harder and more
expensive to test.
• One solution to this problem is to add logic to the
IC so that it can test itself.
• It is a design technique in which parts of a circuit
are used to test circuit itself.
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• An on-chip test generator applies test patterns to
the circuit under test.
• The resulting output is observed by the response
monitor, which produces an error signal if an
incorrect output pattern is detected.
• BIST is often used for testing memory.
• BIST controller is Hardware used to activate self
test simultaneously on all PCBs
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Built-in Self-test

• Convert each flip-flop to a scan register

–Only costs one extra multiplexer
• Normal mode: flip-flops behave as usual
• Scan mode: flip-flops behave as shift register

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• Built-in self-test lets blocks test themselves
– Generate pseudo-random inputs to comb. logic
– Combine outputs into a syndrome
– With high probability, block is fault-free if it produces the
expected syndrome

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• Linear feedback shift registers (LFSRs) are often used
to generate test patterns
• An LFSR is a shift register whose serial input bit is a
linear function of some bits of the current shift register
content

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PRSG
• Linear Feedback Shift Register
– Shift register with input taken from XOR of state
– Pseudo-Random Sequence Generator
Step Q
0 111
CLK
1
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D 2
3
4
5
6
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Step Q
0 111
CLK
Q[0] Q[1] Q[2]
1 110
Flop

Flop

Flop
D D D
2
3
4
5
6
7
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Step Q

CLK
0 111
Q[0] Q[1] Q[2] 1 110
Flop

Flop

Flop
D D D
2 101
3
4
5
6
7
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Step Q
CLK 0 111
Q[0] Q[1] Q[2]
1 110
Flop

Flop

Flop
D D D

2 101
3 010
4
5
6
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Step Q
CLK 0 111
Q[0] Q[1] Q[2] 1 110
F lo p

F lo p

F lo p
D D D
2 101
3 010
4 100
5
6
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Step Q
CLK 0 111
Q[0] Q[1] Q[2] 1 110
Flop

Flop

Flop
D D D
2 101
3 010
4 100
5 001
6
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Step Q
CLK
Q[0] Q[1] Q[2]
0 111

Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5 001
6 011
7
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Step Q

CLK 0 111
Q[0] Q[1] Q[2] 1 110
F lo p

F lo p

F lo p
D D D
2 101
3 010
4 100
5 001
6 011
7 111
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Multiple-Input Signature Register
(MISR)

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• Several types of architectures have been proposed for BIST.

• the STUMPS architecture and

• the BILBO architecture.

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STUMPS

• Self-Testing Using an MISR

and Parallel SRSG.

• SRSG, in turn, stands for Shift

Register Sequence Generator.
• STUMPS is a BIST architecture
that uses scan chains.

• An overview of the STUMPS

architecture is shown in
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• A pseudo-random pattern generator feeds test stimulus to the scan
chains, and after a capture cycle, the test response analyzer receives the
test responses.

• The test procedure in STUMPS is the following:

1. Scan in patterns from the test pattern generator (LFSR) into all scan
chains.
2. Switch to normal function mode and clock once with system clock.
3. Shift out scan chain into test response analyzer (MISR) where test
signature is generated.

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BILBO

• Built-in Logic Block Observer

– Combine scan with PRSG & signature analysis
D[0] D[1] D[2]

C[0]
C[1]

Q[2] / SO

Flop

Flop

Flop
SI 1

0 Q[0]
Q[1]

M ODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1

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• In BILBO schemes, the scan register is modified
so that parts of the scan register can serve as a state
register, pattern generator, signature register, or
shift register.

• When used as a shift register, the test data can be

scanned in and out in the usual way.

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• During testing, part of the scan register can be used as a
pattern generator (PRPG) and part as a signature register
(MISR) to test one of the combinational blocks.

• The roles can then be changed to test another

combinational block.

• When the testing is finished, the scan register is placed

in the state register mode for normal operation.
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• After the BILBO registers are initialized, since
there is no loading of test patterns as in the case of
scan chains, a test can be applied in each clock
cycle.

• Hence, this is categorized as a test-per-clock BIST

scheme.
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Boundary-Scan Circuitry in A Chip

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Test access port

TAP controller is a synchronous finite

state machine
It responds to change in input signals
TCK, TMS and TRST to TAP and
accordingly controls the sequence of
operation of JTAG

TAP controller is a 16 state finite state

machine which controls the scanning
of data into various registers of JTAG.
The sequence of state transition is
decided b TMS input.
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A test access port (TAP) consisting of :

1. Test data in (TDI),

2. Test data out (TDO),
3. Test mode select (TMS),
4. Test clock (TCK),
5. Test reset (TRST) (optional pin)

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• A test access port controller (TAPC):
• An instruction register (IR)
• Several test data registers
• A boundary scan register (BSR) consisting of boundary
scan cells (BSCs)
• A bypass register (BR)
• Some optional registers (Device-ID register, design
specified registers such as scan registers, LFSRs for
BIST, etc.
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Basic Operations

1. Instruction sent (serially) through TDI into

instruction register.
2. Selected test circuitry configured to respond to the
instruction.
3. Test pattern shifted into selected data register and
applied to logic to be tested

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4. Test response captured into some data register
5. Captured response shifted out; new test pattern
shifted in simultaneously
6. Steps 3-5 repeated until all test patterns are
applied.

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Boundary Scan Cell

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• Bypass register:
• A one-bit register used to pass test signal from a
chip when it is not involved in current test
operation

• Device-ID register:
• For the loading of product information
(manufacturer, part number, version number, etc.)
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Main functions of TAP controller

Providing control signals to

• Reset circuitry
• Load instructions into instruction register
• Perform test capture operation
• Perform test update operation
• Shift test data in and out
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Instruction Set
• BYPASS
Bypass data through a chip
• SAMPLE
Sample (capture) test data into BSR
• PRELOAD
Shift-in test data and update BSR
• EXTEST
Test interconnection between chips of board

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State Diagram of TAP Controller

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Functioning of controller

• Test-Logic-Reset: normal mode

• Run-Test/Idle: wait for internal test such as BIST
• Select-DR-Scan: initiate a data-scan sequence
• Capture-DR: load test data in parallel
• Shift-DR: load test data in series

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• Exit1-DR: finish phase-1 shifting of data
• Pause-DR: temporarily hold the scan operation
(e.g., allow the bus master to reload data)
• Exit2-DR: finish phase-2 shifting of data
• Update-DR: parallel load from associated shift
registers

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Summary
• Think about testing from the beginning
–Simulate as you go
–Plan for test after fabrication

If you don’t test it,

IT WON’T WORK! (GUARANTEED)”
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