CHAPTER Two

THE CENTRAL PROCESSING

UNIT (CPU)
1

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OUTLINE
 2.1 Introduction
 What is an Instruction Set ?
 2.2 Machine Instruction Characteristics
 Elements of Machine Instruction
 Operand Locations
 Instruction Representation
 Instruction Types
 2.3 Instruction Set Design
 Types of Operands
 Types of Operations
 Addressing Mode
 Instruction Format
 2.4 Instruction Cycle
 2.5 Interrupts
 2.6 Instruction Cycle Data Flow
 2.7 Processor Structure and Function
 Processor Organization
 Register Organization

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2.1 INTRODUCTION
 Much of the computer architecture/organization
is hidden from a high level language programmer
 Shouldn’t care what the underlying architecture really is

 What is an instruction set?

 the collection of different instructions that are understood
by a CPU or that the CPU can execute

 Machine Code
 encoded in binary – for machines to work with

 For people: represent by assembly 35

codes
 text – for people to work with
INTRODUCTION…
 Instruction set is a boundary where
 Computer designer and computer programmer can
view
the same machine

 From Designer’s
 It provides the Point of view
functional requirements for the CPU.
Implementing the CPU is a task that in large part involves
implementing the machine instruction set.

 From Assembly Language Programmer’s Point

of view
 It enables to be aware of the register and
memory
structure, 46
 the types of data directly supported by the machine and
 the functioning of the ALU
2.2 MACHINE INSTRUCTION CHARACTERISTICS
 The operation of the CPU is determined by
the instructions it executes

 We will investigate
 the design of the instruction set
 The impact of the set on the design of the
overall computer system

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ELEMENTS OF A MACHINE INSTRUCTION
 Each instruction must contain all the information
required by the CPU for execution

 These elements are :

 Operation code (Op code)
 Specifies the operation to be performed
 Do this operation

 Source Operand(s) reference(s)

 Specifies a register or memory location of operand data
 With this/these operands

 An operation may involve one or more source operands

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 Inputs for the operation specified
ELEMENTS OF A MACHINE INSTRUCTION…
 Result Operand reference
 Where the result of the operation should be placed ?
 Put the answer here

 Next Instruction reference

 From where to fetch the next instruction
 When you have done that, do this...

 In most cases not explicitly stated in the instruction

 Implicitly the next instruction, the one that

logically follows the current one in the program

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OPERAND LOCATIONS
 Where Can Operands Be?
 Source and result operands can be in one of the three
areas:
 Main memory
 Memory address must be supplied

 CPU register

 Implicitly referenced, if only one register exist

 Explicitly using its unique number, if

more than one register exists
 I/O device

 Specify the I/O device for the operation

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INSTRUCTION REPRESENTATION
 With in a computer, each instruction is
represented by sequence of bits
 Each instruction has a unique bit pattern

 E.g 0001 – load, 0010- store and 0101- add

 Instruction divided into fields

 Corresponding to the constituent elements
of the
instruction
 E.g. A simple instruction format

 With most instruction set, more than one format is used 9

SIMPLE INSTRUCTION FORMAT

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INSTRUCTION REPRESENTATION…
 Difficult for the programmers to deal
with binary representation of machine
instruction
 Hence, it is common to use a symbolic
representation of machine instruction
 Opcodes
Represented by abbreviations called mnemonics --- that

indicate the operation
 Operands
 Also represented symbolically

 Example
 ADD R, Y

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INSTRUCTION REPRESENTATION…

 Itis possible to write a machine language

program in symbolic form. How?
A simple program accepts this symbolic input ,convert
opcode and operand references to binary form and
construct binary machine instruction

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Consider a high-level language instruction that could be
expressed in a language such as BASIC or FORTRAN.
For example, X=X+Y
This statement instructs the computer to add the value stored in
Y to the value stored in X and put the result in X. How might
this be accomplished with machine instructions?
Let us assume that the variables X and Y correspond to locations
513 and 514. If we assume a simple set of machine instructions,
this operation could be accomplished with three instructions:
1. Load a register with the contents of memory location 513.
2. Add the contents of memory location 514 to the register.
3. Store the contents of the register in memory location 513.

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INSTRUCTION TYPES
 An instruction set must be functionally complete
 Sufficient enough to express any of the instructions
from a high level language

 Categories of instruction types

 Data processing
 Arithmetic and logic instructions
 Data storage
 Memory instructions
 Data movement
 I/O instructions
 Control
 Test and
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branch
instructions
 Program flow
2.3 INSTRUCTION SET DESIGN
 One of the most interesting and analyzed aspects
of computer design
 A very complex task

 Because it affects so many aspects of the

computer system
 Instruction set
 Boundary where computer designer
Computer programmer can and view
machine the
 same
Programmer’s means of controlling the CPU
 Programmers requirement must be considered in designing
the instruction set
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INSTRUCTION SET DESIGN …
 Most important issues related the design of
instruction
to set includes:
 Operation repertoire/list
 How many ops?
 What can they do?
 How complex are they?
 Data Types
 Built-In Data types supported
 Instruction formats
 How to encode as binary values
 Length of op code field
 Number of addresses
 Registers
 Number of CPU registers available
 Which operations can be performed on which registers? 16
 Addressing modes
TYPES OF OPERAND
 Machine instructions operate on data
 Categories of data
 Numbers
 Signed Integer / Unsigned Integer / Floating Point

 Characters

 ASCII, Unicode etc.

 Logical Data

 Bits or flags

 A group of bit where each bit has information

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TYPES OF OPERATIONS
 Different machines support different opcodes:
 Data Transfer
 Arithmetic
 Logical
 Conversion
 I/O
 System Control
 Transfer of Control

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DATA TRANSFER
 Most fundamental type of instructions
 Must specify the following things
 Location of source and destination operands
 memory, register …
 Length of data to be transferred
 Full word, half word …
 E.g.
 Move, Store, Load, Push, Pop
 In terms of CPU action
 data transfer operations are the simplest type

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ARITHMETIC
 Performed by ALU
 Basic arithmetic operations provided by
most
machines are:
 Add, Subtract, Multiply, Divide
 Signed Integer
 Floating point

 May include
 Increment
 Decrement

 Negate
Absolute
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LOGICAL
 Operations that manipulate individual bits of a word
 Bitwise operations
 AND, OR, exclusive-OR (XOR)
 NOT (one’s complement)
 In addition a variety of shifting and rotating functions
 Logical shift
 Shifts bits of word either to the left or right
 On one end the bit shifted out is lost
 Arithmetic shift
 Treats the data as a signed integer and does not shift the sign bit
 Rotate/Cyclic shift
 Preserves all of the bits being operated on

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SHIFT AND ROTATE OPERATIONS
0

logical
shift
shift in 0

arithme
tic
shift
keep sign !

rotate
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CONVERSION
 Change the format of data or operate on
the format of data
 Binary to Decimal
 ASCII to EBCDIC

 E.g. Binary to BCD

 binary 00001111 (1510)
 packed BCD 0001 0101
1

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INPUT/OUTPUT
 Transfer data
 from the computer to peripheral devices
 From peripheral devices to the computer system

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SYSTEM CONTROL
 Reserved for use by the operating system
 Instructions executed while the processor is in
certain privileged mode
 Privileged instructions
 CPU needs to be in specific state

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TRANSFER OF CONTROL
 Alter the flow of program
 i.e. change the sequence of instruction execution
 Update the PC to a specific address
 Most common such type of operations are:
 Branch, Skip, Procedure call

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TRANSFER OF CONTROL…
 Branch
 Also called jump instruction
 Its operand is the address of the next instruction to be fetched
and executed
 Two types of branches
 Conditional and Unconditional
 Conditional Branch
 A branch is made if certain condition is met
 E.g.
 BRP X
 Branch to instruction at location X if result is positive
 BRZ X
 Branch to instruction at location X if result is zero
 BRE R1,R2,X
 Branch to X if contents of R1 is equal to contents of
R2
 Unconditional branch
 E.g. 27
 BR X
 Branch to instruction at location X
TRANSFER OF CONTROL…
Branch Instructions

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TRANSFER OF CONTROL …
 Skip
 Implies that the next instruction be skipped
 Contains an implied address
 Can be of two types:
 Unconditional
 Skip (i.e. unconditionally increment PC to skip the next

instruction)
 Conditional

 Test some condition and skip if met/satisfied

 E.g. Increment and skip next instruction if result is

zero ISZ R1  increment & skip if zero

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ADDRESSING MODES
 The manner in which each address field
specify operand location

 Notations:
 A = Contents of an address field in the instruction
 R = Contents of an address field in the instruction that refers to a
register
 (X) = Contents of memory location X or register X
 EA =Effective address of the location containing the referenced
operand

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ADDRESSING MODES…
 Types of addressing modes
 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement
 Stack

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IMMEDIATE ADDRESSING
 The instruction itself contains the operands value
 Operand is part of instruction

 Operand = A
 E.g. ADD 5
 Add 5 to contents of accumulator
 5 is operand

 No additional memory reference required

after the fetch of the instruction itself
 The value that can be specified is limited
 Size/value of the operand is limited/limited range
 Fast 32
IMMEDIATE ADDRESSING DIAGRAM

Opcode Operand

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DIRECT ADDRESSING
 Address field contains address of operand
 Effective address EA = A
 Operand = (A)
 E.g. ADD A
 Add contents of memory location A to accumulator
 One more memory access needed to fetch the operand
 No additional calculations required to work out
effective address
 Number of memory locations can be referenced,
that limited, due to limited width of
the field
 Common
 Limited addressgeneration
on earlier space of computers
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DIRECT ADDRESSING DIAGRAM
Opcode A
Memory

Operand

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INDIRECT ADDRESSING
 A (the address field) refers to a memory location
which contains the address of operand
 Multiple (two) memory accesses to find
operand
 Fetch EA
 Fetch operand
 Access the memory twice, hence slower
 EA = (A)
 Operand = ((A))
 E.g. ADD (A)
 Look in A, find address (A) and look there for operand
 Range of EA increased
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 Large address space
 2n ,where n = word length
INDIRECT ADDRESSING DIAGRAM

Opcode A
Memory

Operand

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REGISTER ADDRESSING
 Similar to direct addressing
 The address field refers to a register than a main memory address
 EA = R
 Operand = (R )
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
 No memory access required
 Very fast execution
 Very limited address space
 Small number of registers can be referenced
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REGISTER ADDRESSING DIAGRAM

Opcode R
Registers

Operand

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REGISTER INDIRECT ADDRESSING
 Similar to indirect addressing mode
 Operand is in memory pointed to by contents
of
register R
 EA = (R)

 Operand =((R ))

 Large address space (2n)

 Where n is the width of the register
 Address space limitation overcome
 Uses one less memory access than
indirect addressing 40
REGISTER INDIRECT ADDRESSING
DIAGRAM
Opcode R
Memory

Registers

Operand

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DISPLACEMENT ADDRESSING
 Very powerful addressing mode
 Combines
 direct addressing and
 Register indirect addressing
 Instruction needs to have two address fields
 At least one of which is explicit
 EA = A + (R)
 Address field hold two values
 A = base value
 R = register that holds displacement
 or vice versa 41
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DISPLACEMENT ADDRESSING DIAGRAM

Instruction
Opcode R A
Memory
Registers

+
Operand

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RELATIVE ADDRESSING
 A version of displacement addressing mode
 Implicitly references the PC register
 R = Program counter, PC
 EA = A + (PC)
 Saves bits

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BASE-REGISTER ADDRESSING
 Referenced register contains memory address
 R holds pointer to base address

 Address field contains the displacement

from that address
 A holds displacement

 Exploits locality of memory references

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INDEXED ADDRESSING
 Address field contains memory address
 A = base
 The referenced register contains a
displacement from that address
 R = displacement
 EA = A + ( R )
 Good for arrays and performing accessing
iterative operations
 Auto indexing
 increment and decrement

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INDEXED ADDRESSING…
 Combinations
 Indirect addressing with
indexing
 Post indexing
 The indexing performed after the indirection
 EA = (A) + (R)
 Good to access a block of data of a fixed format
 Pre indexing
 The indexing performed before the indirection
 EA = (A+(R))
 Used to construct a multiway branch table 47
STACK ADDRESSING
 A stack
 The stack mode of addressing is a form of implied
addressing
 The machine instructions need not include a memory
reference but implicitly operate on the top of the
stack

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numerical example
Address Memory
Addressing Mode Effective Address Content of AC
PC = 200 200 Load to AC Mode
Immediate Address Mode 201 500
201 Address = 500
Direct Address Mode 500 800
Indirect Address Mode 800 300 R1 = 400 202 Next instruction
Register Mode 400
Register Indirect Mode 400 700 XR = 100
Relative Address Mode 702 325
399 450
Indexed Address Mode 600 900
Autoincrement Mode 400 700 AC 400 700

Autodecrement Mode 399 450

Numerical Example 500 800

R1 = 400
600 900
500 + 202 (PC)
R1 = 400 (after) 702 325
500 + 100 (XR)
R1 = 400 -1 (prior)
800 300
CPU design plan
 RISC- reduced instruction set computer
 This is small or reduced set of instructions.

 every instruction is expected to attain very small

jobs
 instruction sets are modest and simple

 CISC- complex instruction set computer

 have small programs.
 It has a huge number of compound instructions, which
takes a long time to perform
 single set of instruction is protected in several steps
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Comparison b/n CISC and RISC

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INSTRUCTION FORMAT
 It defines the layout of the bits of an instruction, in
terms of its constituent parts
 More than one format used in a given instruction set
with respect to the operand fields in the instructions.

Opcode Operand(s) or Address(es)

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Instruction Formats
 Three-Address Instructions
● ADD R1, R2, R3 R1 ← R2 + R3
 Two-Address Instructions
● ADD R1, R2 R1 ← R1 + R2
 One-Address Instructions
● ADD M AC ← AC + M[AR]
 Zero-Address Instructions
● ADD TOS ← TOS + (TOS – 1)
 RISC Instructions
● Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

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Instruction Formats

Example: Evaluate (A+B)  (C+D)

 Three-Address
1. ADD R1, A, B ; R1 ← M[A] +
M[B]
2. ADD R2, C, D ; R2 ← M[C] +
M[D]
3. MUL X, R1, R2 ; M[X] ← R1 
R2

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Instruction Formats

Example: Evaluate (A+B)  (C+D)

 Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 +
M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 +
M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1

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Instruction Formats

Example: Evaluate (A+B)  (C+D)

 One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC +
M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC +
M[D]
6. MUL T ; AC ← AC 
M[T]
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7. STORE X ; M[X] ← AC
Instruction Formats

Example: Evaluate (A+B)  (C+D)

 Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A +
B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C +
D)
7. MUL ; TOS ←
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(C+D)(A+B)
Instruction Formats

Example: Evaluate (A+B)  (C+D)

 RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1  R3
8. STORE X, R1 ; M[X] ← R1
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2.4 INSTRUCTION CYCLE
 Basic Function
 Execution of a program--- a set of instructions
 Processing of Instruction consists of two steps
 Fetch
 Execute
 Together called an Instruction cycle
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INSTRUCTION CYCLE
 Two steps:
 Fetch
 Execute

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FETCH CYCLE
 Program Counter (PC) holds address of next
instruction to be fetched
 Processor fetches instruction from memory
location pointed by PC
 Increment PC

 Unless told otherwise

 Instruction loaded into Instruction Register (IR)

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EXECUTE CYCLE
 Processor interprets instruction and performs required
actions
 Processor-memory
 data transfer between CPU and main
memory
 Processor -I/O
 Data transfer between CPU and I/O
module
 Data processing
 Some arithmetic or logical operation on
data
 Control
Alteration of sequence of execution


 e.g. jump
 Execution of an instruction may involve a combination of 19
62
above actions
EXAMPLE OF PROGRAM
EXECUTION

20
63
2.5 INSTRUCTION CYCLE DATA FLOW

 The exact sequence of events during an instruction

cycle depends on the design of the CPU
 Ingeneral terms, assuming a CPU that employs
the following registers
 MAR
 MBR
 PC
 IR
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 The possible Data Flow is indicated next
DATA FLOW (INSTRUCTION FETCH)
 Fetch
 PC contains address of next instruction
 Address moved to MAR
 Address placed on address bus
 Control unit requests memory read
 Result placed on data bus, copied to MBR, then to IR
 Meanwhile PC incremented by 1

65
DATA FLOW (FETCH DIAGRAM)

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DATA FLOW (EXECUTE)
 May take many forms
 Depends on instruction being executed

 May include
 Memory read/write
 Input/Output
 Register transfers
 ALU operations

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Instruction pipeline
 organizational approach, which improve the processer
performance
 various stages can be worked on simultaneously

 breaks the instruction cycle up into n tasks, which occur in

sequence.
 There are times during the execution of an instruction when
main memory is not being accessed. This time could be
used to fetch the next instruction in parallel with the execution
of the current one
 Let us consider the following decomposition of the instruction
processing

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 • Fetch instruction (FI): Read the next expected instruction into a
buffer.
• Decode instruction (DI): Determine the opcode and the operand
specifiers.
• Calculate operands (CO): Calculate the effective address of each
source operand. This may involve displacement, register indirect,
indirect, or other forms of address calculation.
• Fetch operands (FO): Fetch each operand from memory.
Operands in registers need not be fetched.
• Execute instruction (EI): Perform the indicated operation and
store the result, if any, in the specified destination operand
location.
• Write operand (WO): Store the result in memory
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Instruction pipeline

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2.6 INTERRUPTS
 Mechanism by which other modules (e.g. I/O)
may
interrupt normal processing of the processor
 Interruption of the normal sequence of execution
 Provided to improve processing efficiency
 Common classes of interrupts
 Program
 e.g. overflow, division by zero
 Timer
 Generated by internal processor timer
 Used in pre-emptive multi-tasking
 I/O
 from I/O controller
 Hardware failure
 e.g. power failure, memory parity error 21
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 Instructioncycle so far consists of the
following sub cycles:
 Fetch
 Execute
 Interrupt

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INTERRUPT CYCLE
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to starting address of interrupt handler
routine
 Process interrupt
 Restore context and continue interrupted 22
73

program
INSTRUCTION CYCLE WITH INTERRUPTS

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TRANSFER OF CONTROL VIA INTERRUPTS

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MULTIPLE INTERRUPTS
 Two approaches to deal with multiple interrupts
 Disable interrupts
 Processor will ignore further interrupts
whilst processing one interrupt
 Interrupts remain pending and are checked after first
interrupt has been processed
 Interrupts handled in sequence as they occur
 Define priorities
 Low priority interrupts can be interrupted by higher
priority interrupts
 When higher priority interrupt has been
processed, processor returns to previous interrupt 25
MULTIPLE INTERRUPTS – SEQUENTIAL
DISABLE INTERRUPTS

77
MULTIPLE INTERRUPTS – NESTED
PRIORITIZED INTERRUPTS

78
TIME SEQUENCE OF MULTIPLE INTERRUPTS

79
DATA FLOW (INTERRUPT)
 Simple and Predictable
 Current PC saved to resumption after
allow interrupt
 Contents of PC copied to MBR
 Special memory location (e.g. stack
pointer) loaded to MAR
 MBR written to memory
 PC loaded with address of interrupt
handling routine
 Next instruction (first of interrupt handler)
can
be fetched 80
DATA FLOW (INTERRUPT DIAGRAM)

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2.7 Processor structure and Function
 Processor Organization
 To understand the organization of the CPU,
recall the requirements placed on the CPU:
 Fetch instruction
 Interpret instruction

 Fetch data

 Process data

 Write data

 To do all these things

 Processor needs to store data temporarily
 Temporary data storage locations --- Registers
--- are needed
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PROCESSOR ORGANIZATION…
 Simplified view of a CPU
 Indicates its connection to the system via the system
bus

83
83
PROCESSOR ORGANIZATION…
 Detailed view of a CPU
 Indicates
 Data transfer and logic control paths
 Internal processor bus

 Used to transfer data b/n the ALU and various registers

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84
REGISTER ORGANIZATION
 Registers
 CPU must have some working space
 Temporary storage
 Top level of memory hierarchy
 Number and function vary between processor
designs
 One of the major design decisions

85
85
REGISTER ORGANIZATION…
 Registers classified into two groups:
 User visible registers:
 Can be referenced by assembly language
 instructions

 Control and status registers:

 Used by control unit to control the operation of
the CPU

86
86
USER VISIBLE REGISTERS
 Can be categorized as follows:
 General purpose registers
 Data registers
 Address registers
 Condition codes

87
87
USER VISIBLE REGISTERS…
 General Purpose Registers
 Can be assigned variety of function by the
programmer
 May be true general purpose
 May be restricted
 May be used for data or addressing

 Data Registers
 Used only to hold data
 Accumulator
88
88
USER VISIBLE REGISTERS…
 Address registers
 Hold addresses
 Can be
 General purpose or
 Devoted to particular addressing mode

 Index registers, stack pointer, segment register

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USER VISIBLE REGISTERS…
CONDITION CODES
 Sets of individual bits , also called flags
 Each bit set by CPUhardware as the result
of operations:
 E.g. Arithmetic operation results could be
 Positive, negative, zero, overflow
 Can be read (implicitly) by programs
 e.g. Jump if zero
 Can not (usually) be set by programs
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CONTROL & STATUS REGISTERS
 Refers to different registers employed to
control the operation of the CPU
 Most not visible to the user
 Register essential during instruction cycle are
 Program Counter (PC)
 Instruction Register (IR)
 Memory Address Register (MAR)
 Memory Buffer Register (MBR)

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CONTROL & STATUS REGISTERS…
 Program Status Word (PSW)
 A register that contain status information
 Usually contains
 Condition codes
 Status information
 Common fields or flags include
 Sign, zero, carry, equal, overflow, supervisor,
interrupt enable/disable
 Note that CPU design and Operating
system design are closely linked

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2.8 INTERCONNECTION STRUCTURES
 A computer consists of a set of components
 All the units must be connected
 The collection of paths connecting various units
 Interconnection structure
 Different type of connection for different type of
unit
 Memory
 Input / Output
 CPU
 There are a number of possible interconnection
structures, the most common are: 29
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 Single and multiple BUS structures
MEMORY CONNECTION
 Receives and sends data
 Receives addresses (of locations)

 Receives control signals

 Read
 Write
 Timing

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INPUT/OUTPUT CONNECTION
 Similar to memory from computer’s viewpoint
 Output
 Receive data from computer
 Send data to peripheral
 Input
 Receive data from peripheral
 Send data to computer

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CPU CONNECTION
 Reads instruction and data
 Writes out data (after processing)

 Sends control signals to other units

 Receives (& acts on) interrupts

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BUS INTERCONNECTION
 What is a BUS ?
 A communication pathway connecting two or more
devices
 Consists of multiple lines, each line capable of transmitting
signals representing binary 1 or binary 0

 Multiple devices can be connected to the same bus

 A shared transmission medium
 A bus that connects major computer components
 System bus

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DATA BUS

 Carries data
 Remember that there is no difference
between “data” and “instruction” at this
level
 Widthis a key determinant of
performance
 8, 16, 32, 64 bit

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ADDRESS BUS
 Identify the source or destination of data
 e.g. CPU needs to read an instruction (data) from a
given location in memory
 Buswidth determines maximum memory
capacity of system
 e.g. 8080 has 16 bit address bus giving 64k address
space

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CONTROL BUS

 Control and timing information

 Memory read/write signal
 Interrupt request
 Clock signals

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0
 Operation of bus
 If one module wishes to send data to another,
it must
 Obtain the use of the bus
 Transfer data via the bus

 Ifone module wishes to request data from

another, it must
 Obtain the use of the bus
 Transfer a request to the other module over the

appropriate control and address lines

 Wait for the second module to send the data

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BUS INTERCONNECTION...
 Single Bus Problems
 If many number of devices are connected to a
single bus, performance will suffer:
Reason
 More devices, the greater the bus length, the
greater the propagation delay
 Co-ordination of bus use can adversely affect
performance
 The bus becomes a bottleneck as the aggregate
data transfer approaches the capacity of bus
 Solutions
• Increasing the data rate that the bus can carry
• Using the wider bus
 Most 39
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systems use multiple buses to overcome 2
these problems
BUS INTERCONNECTION...
 Multiple Buses
 A Traditional Bus
Architecture

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BUS INTERCONNECTION...
 Multiple Buses…
 A High-speed Bus
Architecture

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Evaluate A*B using
a. 3-address format
b. 2-address format
2. Take 10011010
c. Logical right shift(2-bit)
d. Arthimetic left shift(2-bit)
e. Rotate left (2 bit)

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END of Chapter Two

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