Test 101:
Testing and DFT Tutorial
Jeff Rearick
DFT COE
10/04/2001
Testing and Design for Testability
• Why test? How much?
• When do we test?
• What do we test? What do we test for?
• How do we test?
Testing and Design for Testability
• Why test? How much?
• When do we test?
• What do we test? What do we test for?
• How do we test?
Why Bother to Test?
• Because it is difficult to make defect-free chips.
Good Reasons To Do Test
• IC manufacturing is far from perfect
– Even if yield is 99%, defect level is 10k DPM
– This is an unacceptable quality level
• Identifying which chips are bad is non-trivial
– Deserves step(s) in manufacturing process
– Deserves attention during design process
– Deserves automated tools
• Test adds value:
– Increases quality level
– Provides feedback for process improvement
How Much Do We Need to Test?
• Short answer: it depends:
– Can you tolerate shipping defective material?
• Pacemakers, space shuttles, stock exchange
computers, etc. : NO! So, test a lot.
• Give-away toys at ITC exhibitor booths: probably.
– Is your process yield very high?
• Yes? Then there are not many defects; minimize.
• No? Then there are lots of defects, so test a lot.
– Is your profit margin determined by test time?
• Yes? Work on yield, continually optimize test.
• No? Then test to meet your quality specs.
Test Coverage and Quality
(1-C)
Williams & Brown model: DL = 1-Y
DL = Defect Level
Y = functional yield
Reject Rate %
C = defect coverage
1-Y
Big issue: measuring
defect coverage
0
0 100 (approximated as
Coverage % stuck-at coverage )
Test Coverage and Quality : Theory
Reject Rate vs. Fault Coverage
25
20
Reject Rate %
n0=2.5
15 n0=3.0
n0=3.5
n0=4.0
10 Williams-Brown
Stuck-at Coverage
0
0 20 40 60 80 100
Fault Coverage %
Test Coverage and Quality : Data
Reject Rate vs. Fault Coverage
25
20
Reject Rate %
n0=2.5
15 n0=3.0
n0=3.5
n0=4.0
10 Williams-Brown
Stuck-at Coverage
0
0 20 40 60 80 100
Fault Coverage %
Maxwell, ITC’91
Test Coverage and Quality
-(n0-1)C
(1-C)(1-Y)e
Seth & Agrawal model: DL =
Y + (1-C)(1-Y)e -(n0-1)C
n0= average number of
Reject Rate %
1-Y
faults on a bad die
0
0 100
Coverage %
Test Coverage and Quality : Better
Reject Rate vs. Fault Coverage
25
20
Reject Rate %
n0=2.5
15 n0=3.0
n0=3.5
n0=4.0
10 Williams-Brown
Stuck-at Coverage
0
0 20 40 60 80 100
Fault Coverage %
The Cumulative Effect of Low Quality
• If a given component is tested to Q% quality:
n
– A system using n of them has Q % quality
• Examples:
– 90% quality level, 10 uses => 34.87% yield
– 99.9% quality, 100 uses => 90.48% yield
Message:
Test coverage drives quality and profitability!
Testing and Design for Testability
• Why test? How much?
• When do we test?
• What do we test? What do we test for?
• How do we test?
When Do We Test? Process steps:
• During fabrication: optical inspection, parametrics
• Wafer sort: single die or multi-site
• Package test: wire-bond, flip-chip, BGA, etc.
• Board test:
– MCM: Multi-Chip Module
– PCA: Printed Circuit Assembly
– PCB: Printed Circuit Board
• System test: in the assembled unit
• On-line test: during normal circuit operation
Test Early, Test Often
• Production economics: find bad parts early!
wafer wafer pack- pkg board
fab sort aging test build
$x $10x
board system system ship field
test build test return
$100x $1000x $$$x
When To Invest in Test: DESIGN!
• Test problems are very hard to fix after the fact
– Once design is set in stone (er, glass), it is very
expensive to change
– Test history is full of stories of manufacturing
nightmares due to poor testability
• Design-for-testability is a far superior choice
– Consider all phases of testability up front
– Test hardware investment on silicon can be
very cost-effective, but pay attention to area
Testing and Design for Testability
• Why test? How much?
• When do we test?
• What do we test? What do we test for?
• How do we test?
What Do We Test?
Level of Integration Circuit Type
• ASICs, ASSPs
• Discrete devices
• Microprocessors
• Wafers
• Memories
• Bare die
• FPGAs
• Packages
• Analog & RF devices
• MCMs
• Mixed-signal devices
• Boards
• Cores (any of the above)
• Systems
• SOC (System-On-Chip)
Implication: a variety of ATE platforms
What Do We Test For?
Function or Structure or Defects?
Three competing philosophies:
• Functional Test
– Does a device do what it is supposed to do?
• Structural Test
– Does a device contain defect-free structures
and interconnections?
• Defect-based Test
– Is the device statistically indistinguishable from
all the others like it?
The Life Cycle Dimension of Test
• Device characterization vs. production test
– Characterization finds design margins
• Operating points + guardbands (Voltage, Frequency)
• Reliability (ESD, EM, package integrity)
– Production test verifies defect-free manufacture
• Initial tests verify the defect-free operation of device
• Does the device have any latent defects?
– Time-dependent dielectric breakdown
– Metal opens (EM risk)
• Reliability screening: stress, burn-in
Defects, Faults, Errors, Failures
• Defects = physical mistakes (particle, parameter)
• Faults = logical abstractions of defects
– stuck-at faults : line acts as if it is always 0 (1)
– transition faults: line is slow-to-rise (fall)
– bridging faults: two lines are equipotential
• Errors = faults that result in incorrect operation
• Failures = observed errors
A test for a defect excites the corresponding fault,
propagates the error, and observes the failure.
What Constitutes a Good Test?
• Uses several fault models
– Defects manifest themselves many ways
• Obtains high fault coverage
– Exponential effect on quality level
• Covers faults multiple different ways
– 500% is better than 100% (McCluskey ITC’95)
• Uses several different types of patterns
– Scan + Functional + IDDQ + Delay
A Variety of Tests is Best
• Sematech experiment results
Testing and Design for Testability
• Why test? How much?
• When do we test?
• What do we test? What do we test for?
• How do we test?
How Do We Test?
• Test project life cycle: design through obsolescence
design phase: DFT
test generation: ATPG
ATE programming
characterization
production test
design tape 1st production end
start out Si release
project milestones
How Do We Do Test?
design phase: DFT
test generation: ATPG
ATE programming
characterization
production test
Design For Testability
• Purpose: make chip easy to test thoroughly
• Motivation: finish in our lifetime
n
– n-input combinational logic has 2 patterns
m
– m-flop sequential circuit has 2 states
– Possible tests: 2 m+n; possible orders: 2m+n!
• Tricks of the trade: control and observe
– Boundary scan: IEEE 1149.1, P1149.6
– Internal scan (full scan of digital logic)
– Built-in Self Test (BIST)
– ad hoc (test points, etc.)
DFT: Scan Design
• Scan concept: connect all flops into shift register
• Two modes: normal, scan (SCAN_EN signal)
• Transforms sequential circuit into combinational
• EDA tools automate scan insertion and rule
checking
PI PO PI PO
PS NS PPI PPO
logic cloud logic cloud
scan
flip-
flops
DFT for Digital Circuitry : Original
PI combinational logic
PO
D1 D2
Q1 Q2
CK
DFT for Digital Circuitry : Full Scan
PI combinational logic
PO
D1 D2
Q1 Q2
SOUT
SIN
CK
scan_enable
DFT: Scan Test Application
• SCAN_EN = 1; scan data into flops
• Apply Primary Inputs (PIs)
• Observe Primary Outputs (POs)
• SCAN_EN = 0; capture D-input into flops
• SCAN_EN = 1: scan data out of flops; compare
combinational logic
PI PO
D1 D2
Q1 Q2
SOUT
SIN
CK
scan_enable
How Do We Do Test?
design phase: DFT
test generation: ATPG
ATE programming
characterization
production test
Test Generation
• Scan ATPG:
– Inputs: circuit netlist, test procedures
– Outputs: test patterns, fault coverage stats
• Functional test
– Extract from design verification testbenches
– Cycle-ize (to match ATE timing)
• BIST activation tests
• Manual test generation
– Parametric tests, I/O tests, etc.
How Do We Do Test?
design phase: DFT
test generation: ATPG
ATE programming
characterization
production test
ATE program generation
• Translation from source language to tester
– ATPG: STIL, WGL
– Simulation: VCD, various forms of ascii
• Timing waveforms
• Sequencing
• Test flow creation
• Test points and guardbanding
• Binning
How Do We Do Test?
design phase: DFT
test generation: ATPG
ATE programming
characterization
production test
Characterization: Know Your ATE
• ATE features
– Shmoo
• Power supplies
• Clock frequency
– Edge finding
• ATE limitations
– Physical: pin count, vector depth, edge count
– Overall Timing Accuracy (OTA)
• input, output, input-to-output, across testers
– Current limits
– Frequency limits
Example Shmoo Plot
Characterization: Learn Your Chip
• Margins
– Power supplies
– Clock frequency (critical paths)
– I/O edge placement
• Power consumption (dynamic and static)
• Thermal behavior (with temperature forcing)
• QA: ESD, Latch-up, Stress, Burnin, Environmental
• Failure Analysis:
– e-beam probing, emission microscopy, thermal imaging
– strip-back, cross-sectioning
– FIB : Focused Ion Beam rework
How Do We Do Test?
design phase: DFT
test generation: ATPG
ATE programming
characterization
production test
Production Test
• Ideals: repeatability, consistency, uniformity
• Realities: randomness, drift, intermittency
• Tools: quality ATE, calibration, standard parts
• Issues: outsourcing, transfer, platform migration
• Opportunities: yield tuning, process feedback,
quality enhancements
Testing and Design for Testability
• Why test? How much?
• When do we test?
• What do we test? What do we test for?
• How do we test?
We’re done!
