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m1 Verilog (Data Types)

The document discusses data types in Verilog, highlighting built-in types such as variables and nets, and introduces the logic type as an improvement over the classic reg type. It also covers two-state types, fixed-size arrays, packed and unpacked arrays, dynamic arrays, and queues, emphasizing their usage and advantages in simulation. Overall, it provides an overview of how these data types enhance performance and memory efficiency in design modeling.

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5 views16 pages

m1 Verilog (Data Types)

The document discusses data types in Verilog, highlighting built-in types such as variables and nets, and introduces the logic type as an improvement over the classic reg type. It also covers two-state types, fixed-size arrays, packed and unpacked arrays, dynamic arrays, and queues, emphasizing their usage and advantages in simulation. Overall, it provides an overview of how these data types enhance performance and memory efficiency in design modeling.

Uploaded by

inchara27s
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Data Types

1. Built-in Data Types

 Verilog-1995 has two basic data types: variables (reg) and nets

 Variables can be unsigned or signed

 A net is used to connect parts of a design such as gate primitives and module instances

 The logic type


 Two-state types

Vidyavardhaka College of Engineering 1


The logic type
• Verilog Improves the classic reg data type the new name logic

Rather than trying to choose between reg and wire, declare all
your signals as logic

The one limitation is that a logic variable cannot be driven by multiple drivers
such as when you are modeling a bidirectional bus.
Two-state types
• SV introduces several two-state data types to improve simulator performance and
reduce memory usage, over four-state type
• The simplest type is the bit, which is always unsigned.
• There are four signed types: byte, shortint, int, and longint

• .
Fixed-Size Arrays
• Declaring and Initializing Fixed-Size Arrays
• The Array Literal
• Basic Array Operations – for and foreach
• Basic Array Operations – Copy and Compare
• Bit and Array Subscripts, Together at Last
• Packed Arrays
• Packed Array Examples
• Choosing Between Packed and Unpacked Arrays
i.Declaring and Initializing Fixed-Size Arrays
ii.The Array Literal
iii .Basic Array Operations – for and foreach
Basic Array Operations – Copy and Compare
Bit and Array Subscripts, Together at Last
Packed Arrays
• The entire value is divide it into smaller elements.
• For example, you may have a 32-bit register
• That sometimes you want to treat as four 8-bit values and at other
times as a single, unsigned value
Packed Array Examples
Choosing Between Packed and Unpacked
Arrays
• A packed array is handy
• If you need to convert to and from scalars. For example, you might
need to reference a memory as a byte or as a word.
Dynamic Arrays
• System Verilog provides a dynamic array that can be allocated and
resized during simulation and so your simulation consumes a minimal
amount of memory.
• A dynamic array is declared with empty word subscripts []. This
means that you do not specify the array size at compile time; instead,
you give it at run-time.
• The array is initially empty, and so you must call the new[] constructor
to allocate space, passing in the number of entries in the square
brackets
Queues

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