DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

HERITAGE INSTITUTE OF TECHNOLOGY

LABORATORY MANUAL

PAPER NAME: DIGITAL SYSTEMS DESIGN LABORATORY

PAPER CODE: ECE2152

(Witheffectfromtheacademicyear2023 onwards)

DEPARTMENT OF
ELECTRONICSANDCOMMUNICATIONENGINEERING

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

Table of Contents

1. Mission, Vision, PEO, PO, PSO of the Department ………………….………………03

Departmental Mission ……………………………………………………..03
Departmental Vision …………………………………………………….03
Program Educational Objective……………………………………………04
Program Outcome ……………………………………………………..05
Program Specific Outcome ………………………………………………..06

2. Course & Outcomes………………….…………………………………………….…07

Course structure ……………………...……………………………………07
Course Outcome .………………………………………………………….07
List of experiments ………………………………………………………...07

3. Laboratory Experiments………………………………………………….………….09

4. Appendix I : Mapping between Experiments and CO ……………………….…….

5. Appendix II. Course Articulation Matrix…………………………………………...

6. Appendix III: Data Sheets…………………………………………..………………

7. Appendix IV: Evaluation Scheme & Rubrics for Assessment …………………..

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

Vision of Electronics and Communication Engineering Department

The degree holders of the Department will carry the image of the institute and the department
in India and the World through their commitment and success. They will prove themselves to
be good, sincere and successful professionals and teachers. They will prove themselves as
good, caring and responsible citizens.

Mission of Electronics and Communication Engineering Department

Students with degrees from Electronics and Communication Engineering (ECE) Department of
Heritage Institute of Technology will

1. Acquire specialized knowledge in the desired domains

2. Be able to analyze a problem in the given areas and be able to solve it in efficient
manner.
3. Have confidence and knowledge to start new business activities and show
entrepreneurship skills.
4. Develop passion for more studies and R & D.
5. Inherit leadership qualities for society and workplace.

Program Educational Objectives of Electronics and Communication

Engineering Department

The graduate students with the B.Tech. (Electronics and Communication Engineering), degree
from Heritage Institute of Technology, Kolkata are expected to attain the following after a few
years of getting this degree:

They will attain:

1. Strong foundation: establish their ability to analyze and synthesize current Electronics
and Communication Engineering practices by assimilating its basic and advanced approaches
on way to become successful professionals in industries.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

2. Critical & Innovative Thinking: prove their research orientation by their ability to
handle versatile problems in Communication and related field by virtue of their knowledge
acquired in course of the degree.
3. Leadership, coordination & Group Activity: demonstrate their ability to work in
teams. They will prove themselves as good natured and well - behaved members of working
teams as well as leaders in various diverse industries.
4. Implementation of knowledge gained through interaction & effective
communication skills in work places: show their learning and teaching abilities and their
communication efficiency in their work places

Program Outcome & Program Specific Objective

Program Outcomes :

Engineering Graduates will be able to:

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.

PO2: Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.

PO3: Design/development of solutions: Design solutions for complex engineering problems

and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.

PO4 : Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
PO6 : The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

PO9: Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.

PO11: Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

PO12: Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological change.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

Program Specific Outcomes:

The graduates of the department will attain:

PSO1: The ability to absorb and apply fundamental knowledge of core Electronics and
Communication Engineering subjects in the analysis of various types of integrated electronic
systems as well as to interpret and synthesize the experimental data leading to valid
conclusions.

PSO2: Competence in using electronic modern IT tools (both software and hardware) for the
design and analysis of complex electronic systems in furtherance to research activities.

PSO3: The capability to apply the concepts of Electronics and Communication Engineering to
design and develop a variety of components and systems for applications including, but not
limited to, signal processing, Communication, Embedded systems, VLSI and control system.

PSO4: Excellent adaptability to changing work environment, good interpersonal skills as a

leader in a team in appreciation of professional ethics and societal responsibilities.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

Syllabus of Digital Systems Design Laboratory

Course Name: Digital Systems Design Lab
Course Code:ECE2152
Contact L T P Total Credit
Hours per Points
week 0 0 2 2 1

Course Outcomes:
The students after finishing this course will be able to :
ECE2152.1. Design code converters.

ECE2152.2. Design arithmetic circuits.

ECE2152.3. Design combinational logic circuits.

ECE2152.4. Realize flip-flops and counters.

List of Experiments:

1. Realization of basic gates using Universal logic gates.

2. Realization of code conversion circuits - BCD to Excess-3 and vice-versa.
3. Construction of simple arithmetic circuits - Adder, Subtractor.
4. Design of Parity Bit Generator and Checker circuits.
5. Construction of Decoder circuit using logic gates.
6. Construction of Multiplexer circuit using logic gates and realization of different
combinational logic
circuits using Multiplexer.
7. Design of 2-Bit Comparator Circuit.
8. Realization of RS, D and JK flip-flops using universal logic gates.
9. Realization of Asynchronous Up or Down counter.
10. Realization of Synchronous Up or Down counter.
11. Realization of Ring and Johnson’s counters.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

DIGITAL SYSTEMS DESIGN LAB (ECEN2152)

Contents:
EXPERIMENT
EXPERIMENT NAME
NO
Realization of basic gates using Universal
1
logic gates
Code conversion circuits- BCD to Excess-3
2
and vice versa

3 4-bit parity generator & comparator circuits

Construction of simple arithmetic circuits-

4 Adder, Substractor.

Construction of simple Decoder &

5 Multiplexer circuits using logic gates.

Realization of different combinational

6 circuits using Multiplexers.

Realization of RS, JK, and D flip-flops using

7 Universal logic gates.

Realization of Asynchronous Up/Down

8 counters.

Realization of Synchronous Up/Down

9 counters.

Design of Sequential Counter with irregular

10 sequences.

11 Realization of Ring and Johnson’s counters.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 01
REALIZATION OF BASIC GATES USING
UNIVERSAL LOGIC GATES
 
OBJECTIVE:
The purpose of this experiment is to verify the conversion of any gate using only
universal logic- gates.

 
BASIC LOGIC GATES USING NAND LOGIC

LOGIC DESIRED GATE NAND CONSTRUCTION

TRUTH TABLE
GATE
Input A Input B Output
NAND 0 0 1
0 1 1
1 0 1
1 1 0
Input A Output
NOT 0 1
1 0
Input A Input B Output
AND 0 0 0
0 1 0
1 0 0
1 1 1
Input A Input B Output
0 0 0
OR 0 1 1
1 0 1
1 1 1
Input A Input B Output
0 0 1
NOR 0 1 0
1 0 0
1 1 0
Input A Input B Output
0 0 0
XOR 0 1 1
1 0 1
1 1 0

Input A Input B Output

1
0 0

XNOR 0
0 1

0
1 0

1 1 1

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
BASIC LOGIC GATES USING NOR LOGIC

LOGIC DESIRED GATE NOR CONSTRUCTION

TRUTH TABLE
GATE
Input Input Outpu
t
A B
NAND 0 0 1
0 1 1
1 0 1
1 1 0
Input A Output
NOT 0 1
1 0
Input Input
Outpu
t
A B
AND 0 0 0
0 1 0
1 0 0
1 1 1
Input Input
Outpu
t
A B
0 0 0
OR
0 1 1
1 0 1
1 1 1
Input Input Outpu
t
A B
0 0 1
NOR
0 1 0
1 0 0
1 1 0
Input Input Outpu
t
A B
0 0 0
XOR
0 1 1
1 0 1
1 1 0
Outpu
Input Input t
A B
1
0 0

XNOR 0
0 1

0
1 0

1 1 1

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand As Required
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7400 NAND Gate 2
7) IC 7402 NOR Gate 2

 
 PROCEDURE:

1) Draw the NAND & NOR equivalent circuit of the basic gates and identify the pin no. of
each IC
2) Construct the circuit in Digital Trainer Kit / Bread Board using the specified IC and
connecting wires
3) Connect +5V power supply, Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 02
Code conversion circuits
BCD toExcess-3 and vice-versa.

 
OBJECTIVE:

To design and implement 4-bit

1) BCD to excess-3 code converter
2) Excess-3 to BCD code converter
 
THEORY:

While converting from BCD to Exces-3, the circuit accepts 4 bit BCD data as input and
generates 4 bit Exces-3 data. In BCD only 0 to 9 are valid inputs and 10 to 15 treated as
don't care combinations.

During Exces-3 to BCD conversion, the valid inputs combinations are from 3 to 12 while
0, 1, 2, 13, 14, 15 are don't care condition.

The input variable are designated as B3, B2,B1, B0 and the output variables are
designated as E3,E2,E1, E0. From the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A two- level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

  
BCD TO EXCESS-3 CONVERTER
 
TRUTH TABLE:
BCD input Excess – 3 output
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
K-Map for E3:

E3=B3+B2(B1+B0)

 
K-Map for E2:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
K-Map for E1:

 
K-Map for E0:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

LOGIC DIAGRAM :

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXCESS-3 TO BCD CONVERTER :

 
TRUTH TABLE:
Excess – 3 Input BCD Output
E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

Derive the equations of B3, B2, B1 and B0 using K maps. The expressions are as follows:

B3 = E3E2 + E3E1E0
̅̅̅ ̅̅̅̅̅̅ ̅̅̅ ̅̅̅̅̅̅ ̅̅̅ (̅̅̅̅̅̅ ̅̅̅)̅̅̅

B1 = E1 E0
̅̅̅

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
LOGIC DIAGRAM:

E0 B0

E1 B1

E2 B2

E3 B3

 
APPRATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand As Required
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7486 X-OR GATE 1
7) IC 7408 AND GATE 1
8) IC 7432 OR GATE 1
9) IC 7404 NOT GATE 1

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

  
PROCEDURE:
1) Draw the required circuits of the code conversion and identify the pin no. of each
IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified
IC and connecting wires
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 03
DESIGN AND IMPLEMENTATION OF PARITY
GENERATOR AND CHECKER&MAGNITUDE
COMPARATOR


OBJECTIVE: 
To design and implement
1) 3 – bit odd parity generator and checker
2) 2 – bit magnitude comparator using basic gates.

 
 3- BIT ODD PARITY GENERATOR AND CHECKER

 
THEORY:
A parity bit is used for the purpose of detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to make the
number of 1’s either odd or even. The message including the parity bit is transmitted and
then checked at the receiving end for errors. An error is detected if the checked parity
does not correspond with the one transmitted. The circuit that generates the parity bit in
the transmitter is called a parity generator and the circuit that checks the parity in the
receiver is called a parity checker.

In even parity the added parity bit will make the total number of 1’s even and in odd
parity the added parity bit will make the total number of 1’s odd.
In a three bit odd parity generator the three bits in the message together with the parity
bit are transmitted to their destination, where they are applied to the parity checker
circuit. The parity checker circuit checks for possible errors in the transmission.
Since the information was transmitted with odd parity the four bits received must have an
odd number of 1’s. An error occurs during the transmission if the four bits received have
an even number of 1’s, indicating that one bit has changed during transmission. The
output of the parity checker is denoted by PEC (parity error check) and it will be equal to
1 if an error occurs, i.e., if the four bits received has an even number of 1’s.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 ODD PARITY GENERATOR

 
TRUTH TABLE:

INPUT
OUTPUT
(3-bit message)
( Odd Parity bit)
A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Derive the expression of P using K-map.

 
LOGIC DIAGRAM: ODD PARITY GENERATOR

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
ODD PARITY CHECKER

INPUT OUTPUT
( four bit message Received) (Parity error check)
A B C P X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

From the truth table the expression for the output parity checker bit is,
X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15)
Derive the expression of X using K-map.

 
LOGIC DIAGRAM: ODD PARITY CHECKER

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
2 – BIT MAGNITUDE COMPARATOR USING BASIC GATES

 
THEORY:
A magnitude comparator is a combinational circuit that compares two numbers A and B.
The outcome of the comparator is specified by three binary variables that indicate
whether A>B, A=B or A<B.

A =A1A0
B =B1B0
  
2 BIT MAGNITUDE COMPARATOR
 
TRUTH TABLE

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
K- MAP:

Derive the expression of (A=B) using Boolean algebra as there are 4 isolated 1’

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

LOGIC DIAGRAM:

A<B

A=B

A>B

 
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7486 X-OR GATE 1
7) IC 7408 2 Input AND GATE 1
8) IC 7432 OR GATE 1
9) IC 7404 NOT GATE 1
10) IC 7411 3 Input AND GATE 2

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
PROCEDURE:

1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC
and connecting wires
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 04
CONSTRUCTION OF SIMPLE ARITHMETIC
CIRCUITS :ADDER, SUBTRACTOR.

To design and implement the following circuit using logic gates-

1) Half- Adder
2) Full- Adder using Half- Adder
3) Half- Subtractor
4) Full- Subtractor using Half- Subtractor
  
HALF - ADDER:
 
THEORY:

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.
 
TRUTH TABLE:
A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0


K-M

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
 FULL- ADDER USING HALF ADDER :

 
THEORY:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time but a half
adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output
will be taken from OR Gate.
 
TRUTH TABLE:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Derive the expression for Sum and carry required to realize the circuit

S = A ⊕ B ⊕ Cin

Cout = AB + Cin(A ⊕ B)

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

LOGIC DIAGRAM:
´) ( ´ ´)

( )

  
HALF -SUBTRACTOR:
 
THEORY:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.
 
TRUTH TABLE:

A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Difference = A ⊕ B

Borrow = 𝐴̅̅̅𝐵
̅̅̅

LOGIC DIAGRAM:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
 FULL -SUBTRACTOR USING HALF SUBTRACTOR :

 
THEORY:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put
together gives a full subtractor .The first half subtractor will be C and A B. The output
will be difference output of full subtractor. The expression AB assembles the borrow
output of the half subtractor and the second term is the inverted difference output of first
X-OR.

 
TRUTH TABLE:

A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Derive the expressions for Difference and Borrow required to realize the circuit;

LOGIC DIAGRAM:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

́ (̅̅̅ )

 
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7408 2 INPUT AND GATE 1
7) IC 7432 OR GATE 1
8) IC 7404 NOT GATE 1
9) IC 7486 XOR GATE 1

 
PROCEDURE:

1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC and
connecting wires.
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 05
CONSTRUCTION OF SIMPLE DECODER &
MULTIPLEXER CIRCUITS USING LOGIC GATES
 
OBJECTIVE:
To design and implement
1) 2 to 4 Line Decoder,
2) 4:1 Multiplexer.
  
2 TO 4 LINE DECODER:
 
THEORY:
A decoder is a circuit that changes a code into a set of signals. It is called a decoder
because it does the reverse of encoding, but we will begin our study of encoders and
decoders with decoders because they are simpler to design. A common type of decoder is
the line decoder which takes an n-digit binary number and decodes it into 2n data lines.
A typical application of a line decoder circuit is to select among multiple devices. A
circuit needing to select among sixteen devices could have sixteen control lines to select
which device should “listen”. With a decoder only four control lines are needed.
 
TRUTH TABLE:

SELECT OUTPUT
LINES
S0 S1
0 0 D0
0 1 D1
1 0 D2
1 1 D3


BLOCK & LOGIC DIAGRAM:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

  
4:1 MULTIPLEXER:
 
THEORY:
Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds
and as such, the device we use to do just that is called a Multiplexer.
The multiplexer, shortened to “MUX”, is a combinational logic circuit designed to
switch one of several input lines through to a single common output line by the
application of a control signal. Multiplexers operate like very fast acting multiple
position rotary switches connecting or controlling multiple input lines called “channels”
one at a time to the output.


TRUTH TABLE:
S1 S0 F
0 0 W
0 1 X
1 0 Y
1 1 Z

̅̅̅ ̅̅̅̅̅̅ ̅̅̅ ̅̅̅

 
LOGIC DIAGRAM:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7411 3 INPUT AND GATE 2
7) IC 7408 2 INPUT AND GATE 1
8) IC 7432 OR GATE 1
9) IC 7404 NOT GATE 1

 
PROCEDURE:

1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC
and connecting wires
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 06
REALIZATION OF DIFFERENT
COMBINATIONAL CIRCUIT USING MUX
  
OBJECTIVE:
1) To design a 8:1 MUX using 4:1 MUX and necessary logic gates
 
THEORY :

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

The 74153 MUX has two separate 2-input/4-row MUXs on it. To create a
single 8-row truth table, we can start by implementing parts of the table on
different MUXs, and then combining the two separate outputs into one output.
... Remember, each strobe turns its MUX on when it is low.

 
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 74153 Dual 4:1 MUX 1
7) IC7404 NOT GATE 1

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 07
REALIZATION OF RS-JK& D FLIP-FLOPS USING
UNIVERSAL LOGIC GATES
 
OBJECTIVE:
To design and implement the following circuit using logic gates-
1) S-R FLIP FLOP
2) J-K FLIP FLOP,
3) D FLIP FLOP

  
S-R FLIP FLOP:
 
THEORY:

The clocked SR flip-flop shown in the figure consist of a basic NOR flip-flop and two
AND gates.. The outputs of two AND gates remain at 0 as long as the clock pulse (or
CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1,
information from the S and R input passes through to the basic flip-flop. With both S=1
and R= 1, the occurrence of a clock pulse causes both outputs to momentarily go to 0.
when the pulse is removed the state of the flip-flop is indeterminate, ie , either state may
result, depending on whether the set or reset input of the flip-flop remains a 1 longer than
the transition to 0at the end of the pulse.

 
STATE TABLE:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

TRUTH TABLE

 
LOGIC DIAGRAM:

  
J-K FLIP FLOP:
 
THEORY:

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only
difference is that the intermediate state is more refined and precise than that of a S-R flip
flop.
The behaviour of inputs J and K is same as the S and R inputs of the S-R flip flop. The
letter J stands for SET and the letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1.
The circuit includes two 3-input NAND gates. The output Q of the flip flop is returned
back as a feedback to the input of the NAND along with other inputs like K and clock
pulse [CP]. So, if the value of CP is ’1′, the flip flop gets a CLEAR signal and with the
condition that the value of Q was earlier 1. Similarly output Q’ of the flip flop is given as
a feedback to the input of the NAND along with other inputs like J and clock pulse [CP].
So the output becomes SET when the value of CP is 1 only if the value of Q’ was earlier
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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

The output may be repeated in transitions once they have been complimented for J=K=1
because of the feedback connection in the JK flip-flop. This can be avoided by setting a time
duration lesser than the propagation delay through the flip-flop. The restriction on the pulse
width can be eliminated with a master-slave or edge-triggered construction.

STATE TABLE:

TRUTH TABLE :

 
LOGIC DIAGRAM:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

Digital Systems & Design Laboratory

  
D FLIP FLOP:
 
THEORY:
The D flip-flop shown in figure is a modification of the clocked SR f flip-flop. The D
input goes directly into the S input and the complement of the D input goes to the R
input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-
flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches
to the clear state.
 
STATE TABLE:

 
LOGIC DIAGRAM:

 
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7408 2 INPUT AND GATE 1
7) IC 7411 3 INPUT AND GATE 1
8) IC 7400 NAND GATE 1
9) IC 7404 NOT GATE 1
10) IC 7402 NOR GATE 1

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

  
PROCEDURE:
1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC and
connecting wires.
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.


CONCLUSION

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 08
REALIZATION OF ASYNCHRONOUS UP/DOWN
COUNTER
 
OBJECTIVE:
To design and realize asynchronous up & down counter.

 
THEORY:
In asynchronous counter the clock is applied to the first flip flop and the output of the
first stage is connected as a clock to the second stage and so on. In the asynchronous
up/down counter a control line M controls the counting sequence. If M=0, the counter
counts in the up direction and if M=1 the counter counts in the down direction.
 
LOGIC DIAGRAM:

 
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7476 Dual JK Flip Flop 2

 
PROCEDURE:

1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC and
connecting wires.
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.


CONCLUSION
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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE


EXPERIMENT 09
REALIZATION OF SYNCHRONOUS UP/DOWN
COUNTER
 
OBJECTIVE:
To design and realize synchronous up & down counter.
 
THEORY:
In synchronous counters, the clock inputs of all the flip-flops are connected together and
are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in
parallel). The circuit below is a 4-bit synchronous counter. The J and K inputs of FF0 are
connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J
and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs
of FF0 and FF1. A simple way of implementing the logic for each bit of an ascending
counter (which is what is depicted in the image to the right) is for each bit to toggle when
all of the less significant bits are at a logic high state. For example, bit 1 toggles when bit
0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when
bit 2, bit 1 and bit 0 are all high; and so on.
Synchronous counters can also be implemented with hardware finite-state machines,
which are more complex but allow for smoother, more stable transitions. Hardware-
based counters are of this type. A simple way of implementing the logic for each bit of
an ascending counter (which is what is depicted in the image to the right) is for each bit
to toggle when all of the less significant bits are at a logic high state
 
LOGIC DIAGRAM:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7404 NOT GATE 1
7) IC 7408 2 INPUT AND GATE 1
8) IC 7432 OR GATE 1
9) IC 7476 Dual JK Flip Flop 2

  
PROCEDURE:
1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC and
connectingwires.
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 10
DESIGN OF SEQUENTIALCOUNTER WITH
IRREGULAR SEQUENCE

 
OBJECTIVE:
To design a sequential counter using J-K Flip flop which counts in the sequence
\ 12571.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
K-MAP:


CONCLUSION

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

EXPERIMENT 11 – REALIZATION OF RING &

JOHNSON’S COUNTER
 
OBJECTIVE:
To design and implement the following circuit using flip-flops -
1) Ring Counter
2) Johnson’s Counter
 
THEORY:
A ring counter is a type of counter composed of a circular shift register. The output of the
last shift register is fed to the input of the first register. There are two types of ring
counters:

A straight ring counter or Over beck counter connects the output of the last shift
register to the first shift register input and circulates a single one (or zero) bit
around the ring. For example, in a 4-register counter, with initial register values
of 1000, the repeating pattern is: 1000, 0100, 0010, 0001, 1000... . Note that  one
 of the registers must be pre-loaded with a 1 (or 0) in order to operate properly.

A twisted ring counter or Johnson counter connects the complement of the output
of the last shift register to its input and circulates a stream of one’s followed by
zeros around the ring. For example, in a 4-register counter, with initial register
values of 0000, the  repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111,
0011, 0001, 0000... .

SEQUENCE TABLE:
Straight ring/Over beck counter Twisted ring/Johnson counter
Clock Clock
Cycle Q0 Q1 Q2 Q3 Cycle Q0 Q1 Q2 Q3
pulse pulse
0 1 0 0 0 0 0 0 0 0
1 0 1 0 0 1 1 0 0 0
I
2 0 0 1 0 2 1 1 0 0
3 0 0 0 1 3 1 1 1 0
I
4 1 0 0 0 4 1 1 1 1
5 0 1 0 0 5 0 1 1 1
II
6 0 0 1 0 6 0 0 1 1
7 0 0 0 1 7 0 0 0 1
8 III 1 0 0 0 8 II 0 0 0 0

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

LOGIC DIAGRAM:

Ring Counter

Johnson’s Counter

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

 
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1) Digital Trainer Kit . 1
2) Bread Board . 1
3) Connecting Wires Single Strand AS REQUIRED
4) Wire Stripper . 1
5) Tweezers . 1
6) IC 7474 Dual D Flip Flop 2

 
 PROCEDURE:


1) Draw the required circuits and identify the pin no. of each IC
2) Construct the circuit in Digital Trainer Kit / bread board using the specified IC and
Connecting wires.
3) Connect +5V power supply, Logical Inputs and Outputs from Trainer Kit.
4) Verify the input/output combinations according to the truth table.

 
CONCLUSION:

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

APPENDIX-I

Datasheets

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

June 1986
Revised March 2000

DM74LS32
Quad 2-Input OR Gate
General Description
This device contains four independent gates each of which
performs the logic OR function.

Ordering Code:
Order Number Package Number Package Description
DM74LS32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

YAB

H  HIGH Logic Level

L  LOW Logic Level

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

September 1986
Revised February 2000

DM7486
Quad 2-Input Exclusive-OR Gate
General Description
This device contains four independent gates each of which
performs the logic exclusive-OR function.

Ordering Code:
Order Number Package Number Package Description
DM7486N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram Function Table

YAB

H  HIGH Logic Level

L  LOW Logic Level

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

September 1986
Revised July 2001

DM7476
Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
General Description negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs
This device contains two independent positive pulse trig- must not be allowed to change while the clock is HIGH.
gered J-K flip-flops with complementary outputs. The J and The data is transferred to the outputs on the falling edge of
K data is processed by the flip-flop after a complete clock the clock pulse. A LOW logic level on the preset or clear
pulse. While the clock is LOW the slave is isolated from the inputs will set or reset the outputs regardless of the logic
master. On the positive transition of the clock, the data levels of the other inputs.
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the

Ordering Code:
Order Number Package Number Package Description
DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram Function Table

H  HIGH Logic Level

L  LOW Logic Level
X  Either LOW or HIGH Logic Level
 Positive pulse data. The J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q0  The output logic level before the indicated input conditions were
established.
Toggle  Each output changes to the complement of its previous level on
each complete active HIGH level clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (HIGH) level.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

APPENDIX-II

Mapping of Experiments with Course Outcome

Experiment
Experiment Name CO 1 CO 2 CO 3 CO 4
No.

Realization of basic gates

1. √
using Universal logic gate

Code conversion circuits-

2. BCD to Excess-3 and vice- √
versa.
4 bit parity generator and
3. √
comparator circuit

1. Construction of simple
4. arithmetic circuits – Adder, √
Subtractor
Construction of simple
5. decoder & multiplexer circuits √
using logic gates
Realization of different
6. combinational circuits using √ √
multiplexers
Realization of RS, JK and D
7. √
FF using universal logic gates
Realization of asynchronous
8. √
up/down counter
Realization of synchronous
9. √
up/down counter
Design of sequential counter
10. √
with irregular sequences
Realization of Ring and
11. √
Johnson counters

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

APPENDIX-III

Course Articulation Matrix

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

APPENDIX-IV

Laboratory Session Frequency 2 per week

Duration of Laboratory Session 2 hours
Continuous Assessment 60 Marks
End Semester Assessment 40Marks

Rubrics Evaluation for Continuous Assessment in Laboratory

Lab Performance + Lab Report + Regularity = 40+10+10 = 60 Marks

Assessment Criteria
Level
Low Medium High Maximum
(0-40%) (41%-70%) (71%-100%) Marks
Parameter
Need total support Need some support
Can apply the engineering
to understand the to understand the
fundamental to understand
circuit and identify circuit and identify
the circuits and identify
the components. the components.
the design system
Need significant Need some support
components to meet the
support to to implement the
specified need.
implement the circuit.
Can implement the circuit
circuit. Identify the
without any support from
Cannot identify problem in the
Laboratory the teachers.
the problem in the circuit but not
Performance Clearly identify the 10
circuit properly. consistently.
(Each problem in the circuit.
Poor in Lack of confidence
experiment) Troubleshoots effectively
troubleshooting. in troubleshooting
and efficiently.
Accuracy in is observed
Results are more than 90%
desired output is Accuracy in results
accurate
poor. is within 80 – 90 %.
Laboratory report is
Laboratory report
Laboratory Laboratory report is according to the given
is not according to
Report according to the format. Key concepts and
the given format 5
(Each given format but not technical aspects of the
and not well
experiment) well prepared. laboratory are clearly
prepared.
described.
Irregular
Not very regular but Reports to the laboratory
Overall attendance and
consistent in the regularly and consistent in 10
Regularity inconsistent in
work. work.
work.

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DIGITAL SYSTEMS DESIGN LABORATORY MANUAL DEPARTMENT OF ECE

Rubrics Evaluation for End Semester Assessment

Experiment done & Viva = 40 Marks

Assessment Criteria
Level
Low Medium High Maximum
(0-40%) (41%-70%) (71%-100%) Marks
Parameter

Ability to carry
out laboratory Performed Completed
Executed perfectly 10
task inaccurately partially
independently

Ability to
explain basic Explained in bit Explained
Explained perfectly 10
topics related to and pieces partially
the course
Partially predict
Partially predict Can predict output
Critical output from given
output from given from given input 10
Thinking input conditions
input conditions conditions
and hints
Difficult to hear Speak with
Communication Clear voice but a
and lack of confidence in clear 10
Skill little nervous
confidence voice

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