Queue
module QueueExample;
int queue[$]; // Dynamic queue
initial begin
queue.push_back(10);
queue.push_back(20);
queue.push_back(30);
$display("Queue: %p", queue);
$display("Popped: %0d", queue.pop_front());
$display("Queue: %p", queue);
queue.push_back(40);
$display("Queue: %p", queue);
end
endmodule
Memory
module MemoryExample;
int mem[] = new[5];
initial begin
foreach (mem[i]) mem[i] = i * 10;
$display("Memory: %p, Read mem[2]: %0d", mem, mem[2]);
mem = new[3];
$display("Resized: %p", mem);
end
endmodule
Op:
Memory: {0, 10, 20, 30, 40}
Read mem[2]: 20
Resized Memory:{0, 0, 0}
11. Design a code using associative
array for implementing memory
module MemoryExample;
int mem[int]; // Associative array for memory
initial begin
// Write values to memory
mem[0] = 10;
mem[2] = 20;
mem[5] = 50;
// Read values
$display("Memory: %p", mem);
$display("Read mem[2]: %0d", mem[2]);
// Check if a key exists
if (mem.exists(3))
$display("mem[3] exists");
else
$display("mem[3] does not exist");
end
endmodule
Op
Memory: '{0:10, 2:20, 5:50}
Read mem[2]: 20
mem[3] does not exist
11. Design a SystemVerilog Code Using an Associative Array for
Memory Implementation
module MemoryExample;
int mem[int]; // Associative array for memory
initial begin
mem[1] = 100;
mem[3] = 300;
mem[7] = 700;
$display("Memory: %p", mem);
$display("Read mem[3]: %0d", mem[3]);
if (mem.exists(5))
$display("mem[5] exists");
else
$display("mem[5] does not exist");
end
endmodule
Output:
Memory: '{1:100, 3:300, 7:700}
Read mem[3]: 300
mem[5] does not exist
Key Features:
Uses an associative array (int mem[int];) for memory simulation.
Stores and retrieves values dynamically.
Uses exists() to check if a memory location is allocated.
---
12. Layered Testbench and Its Advantages in Functional
Verification
A layered testbench in SystemVerilog follows a modular structure
to enhance reuse, scalability, and maintainability.
Layers in a Layered Testbench:
1. Test Layer → Defines different test scenarios.
2. Environment Layer → Connects components (agents,
scoreboard, etc.).
3. Agent Layer → Handles the interface between DUT and
testbench.
4. Driver Layer → Sends transactions to DUT.
5. Monitor Layer → Captures and checks DUT responses.
6. Scoreboard Layer → Compares expected vs. actual results.
Advantages:
Reusability → Components can be reused across different tests.
Scalability → Easily extendable for complex designs.
Debugging → Easier to isolate issues due to modularity.
---
13. Difference Between Fixed-Size Arrays, Dynamic Arrays, and
Queues in SystemVerilog
Example:
int arr[5]; // Fixed-size
int dyn[]; dyn = new[10]; // Dynamic array
int queue[$]; queue.push_back(20); // Queue
---
14. SystemVerilog Code Demonstrating Associative Array Usage
module AssocArrayExample;
string employee[string]; // Associative array
initial begin
employee["101"] = "Alice";
employee["102"] = "Bob";
$display("Employees: %p", employee);
if (employee.exists("102"))
$display("Employee 102: %s", employee["102"]);
end
endmodule
Output:
Employees: '{"101":"Alice", "102":"Bob"}
Employee 102: Bob
---
15. Evaluating Verification Guidelines for Testbench Reliability and
Performance
Modularity → Enables better debugging and reuse.
Randomization Constraints → Ensures real-world test scenarios.
Coverage-Driven Verification → Measures test effectiveness.
Assertions & Functional Coverage → Detects corner-case failures.
Reusable Components → Increases efficiency in test development.
Efficient Logging → Helps debugging without excessive overhead.
Impact: Ensures robust and scalable testbenches for complex
designs.
---
16. Justifying User-Defined Structures Over Built-in Data Types in
Complex Verification
Why Use struct Over int or bit?
Better Organization → Groups related variables into a single
entity.
Code Readability → Makes verification code more understandable.
Scalability → Easier to extend for new data fields.
Example:
typedef struct {
int id;
string name;
} Employee;
Employee emp = '{1, "Alice"};
$display("Employee: %p", emp);
Output:
Employee: '{id:1, name:"Alice"}
Benefit: Keeps data structured and modular in verification
environments.
---
17. Comparing Storage Types (Arrays, Queues, Linked Lists) in
SystemVerilog
Example: Queue for FIFO operations
int queue[$];
queue.push_back(10); queue.push_back(20);
$display("Queue: %p", queue); // '{10, 20}
---
18. The Role of Maximum Code Reuse in Large-Scale Verification
Projects
Why is Code Reuse Important?
Reduces Development Time → No need to rewrite common
functions.
Improves Maintainability → Centralized bug fixes.
Enhances Scalability → Easy to extend for new features.
Reduces Errors → Reused, tested modules ensure reliability.
How to Achieve Code Reuse?
Use Object-Oriented Programming (OOP) → Class-based
verification.
Parameterized Testbenches → Easily configurable for different
DUTs.
Reusable Sequences & Drivers → Avoid redundant transaction
definitions.
Layered Architectures → Modular testbench components.
Example of a Reusable Class-Based Transaction:
class Transaction;
rand int addr, data;
constraint valid_range { addr inside {[0:255]}; }
endclass
The above Transaction class can be reused across different
testbenches!
---
Final Thoughts
Associative arrays help implement memory efficiently.
Layered testbenches improve reusability and maintainability.
Fixed, dynamic, and queue-based storage each have specific use
cases.
Code reuse significantly enhances efficiency in large-scale
verification projects.
Would you like any topic explained in more detail?
module AssocArrayExample;
string employee[string]; // Associative array
initial begin
employee["101"] = "Alice";
employee["102"] = "Bob";
$display("Employees: %p", employee);
if (employee.exists("102"))
$display("Employee 102: %s", employee["102"]);
end
endmodule
