Design And Implementation of UART in Verilog

Rajiv Sadriwala Abhay Shah

Department of Electronics and Communication Department of Electronics and Communication
Institute of Technology, Nirma University Institute of Technology, Nirma University
Ahmedabad,India Ahmedabad,India
19bec116@nirmauni.ac.in 19bec119@nirmauni.ac.in

Abstract—Designing a System–on–Chip (SoC) on an FPGA

is becoming increasingly popular in electronic design because
it offers numerous benefits over discrete semiconductor-based
products, including increased speed, lower power consumption,
smaller size, and cheaper cost. The major goal of this paper
is to use Verilog to construct and validate a full-duplex UART
module. It is a serial communication protocol that allows devices
to communicate without the use of a clock signal. It turns parallel
data into serial data and sends it across the network. After
receiving data in serial format, it is transformed into the parallel
format. The baud rate generator, receiver, transmitter, interrupt,
and FIFO modules are all designed as part of the UART.
Verification entails checking the design by setting up a verification
environment that allows the testbench to be reused while also
reducing code complexity. The software implementation of UART
using Verilog HDL is shown in this work. Quartus II simulator
is used for simulation, and it is fully compatible with UART.

I. I NTRODUCTION Fig. 1. Half-Duplex and Full-Duplex mode of UART

UART (Universal Asynchronous Receiver Transmitter) is
a universal serial communication technology that sends data
which is not useful more precisely for communication so
serially from one system to another. It is a piece of computer
we generate different frequencies or low frequencies for our
hardware or an integrated circuit (IC) in a microcontroller
transmitter and receiver and this module also models then to
that controls the computer interface. Both transmission and
do communication on same baud rate and the other modules
reception are possible using UART. Because data transmission
transmitter is used for transmitting the data and receiver is
is asynchronous, there is no need for a clock. The name
used to receive the data.
Universal Asynchronous Receiver Transmitter comes from
While designing we should always ensure that the baud
the fact that the data format and transmission speed can
rate of transmitter and receiver is the same for the successful
be customized. The majority of peripherals communicate in
transmission of data.
parallel data format. UART takes parallel data and converts it
to serial data in the transmitter part before sending it to the • BAUD-RATE GENERATOR: A frequency divider is a
receiver. Before delivering serial data to peripheral devices, baud rate generator. As illustrated in Fig 2, UART fea-
the receiver needs to convert it to a parallel format. UART can tures a customizable baud generator. The processor clock
be configured in two modes also half-duplex and full-duplex. generator provides an input clock, which is divided by a
Half-duplex means a UART can only transmit or receive the divisor stored in the divisor latch to generate a baud clock.
data can’t do both but full-duplex means a UART can receive The baud clock is sixteen times the baud rate, implying
and transmit the data both simultaneously. Thus there is also that data is sent every 16 baud clock cycles. A given
these option of customization in UART hence it is called system clock frequency and the needed baud rate can
Universal. Here in figure 1, we have shown both modes of be used to compute the baud rate frequency factor. The
UART i.e Half-duplex and Full-duplex both. frequency coefficient (M) i.e. count value of the baud rate
generator is :-
II. DESIGN M = System frequency / Factor of baud rate × baud rate
So the design of UART basically requires three building Want to interface to 115200 baud UART for Tx/Rx pair
blocks or sub-modules. The receiver side, the Baud Rate Hence, 50000000 / 115200 = 435 Clocks Per Bit.
generator, and the transmitter side are all part of the UART The frequency coefficient M is not in a round figure in
design. So the need for a Baud rate generator here is as this case. We rely on the fact that the serial interface can
we have a high frequency available on our FPGA board tolerate a few percent of baud rate generation error to
achieve efficiency in FPGA.

Fig. 4. Data Frame of UART

Fig. 2. Basic Block level diagram of the Baud Rate Generator

• RECEIVER: The serial bit stream of data is received by
• TRANSMITTER: The transmitter module is responsible the UART receiver. The data is then converted to parallel
for sending the data serially to the receiver. The parallel format by removing the start and stop bits. Data will be
data is converted into a serial bit stream by the transmitter sampled at a rate set by the baud rate generator, which
module. The transmitter’s architecture will include a is generated at the receiver’s host, in our architecture.
controller, a data register, a data shift register, and a status To ensure that the data is sampled in the midst of a bit
register (bit counter) for counting transmitted bits(reg of time, the sample clock cycle will be counted. The
bitpos). The host CPU provides the input signals, while sampling algorithm must ensure that the initial bit was
the output signals govern data transfer in the UART. Thus correctly received. Create a sample for the data received.
here the transmitter is also responsible for sending the Load the information into a local bus. So now our Verilog
data as per the data frame of the UART. The data frame code for the receiver is also written in FSM fashion. After
of UART says initially when our transmitter is idle then the input data drops low, subsequent samples of value
he will be just passing high pulses but since it wants to 0 will determine the arrival of the start bit. After that,
start communication or data transmission so it will now three further samples will be taken to ensure that a valid
send a low bit pulse then as per the data frame it will start bit has been received. Following that, 8 bits will
send the input data or transmitting data then parity bit if be sampled at roughly the middle of their bit times. The
it is there or else will send the stop bit by sending the receiver state machine in our design has three states: start,
high bit pulse and the maximum number of data bits we data, and stop. The sample clock synchronizes transitions
can transfer in UART are 5-9 data bits including parity between states.
bits. Now in Verilog we wrote our code in a state fashion The machine was put in to start mode when the asyn-
means FSM so we declared four states for the transmitter chronous active low reset was asserted. It’s also the
first is the idle state means it not sending any data then the default condition. It will stay till data input is set to active
start state means sending the start bit then the data state low. The machine transitions to state commencing if the
means sending data bits and the parity bit then finally they data input is active high. The machine samples data input
stop state means sending the stop bit. The state diagram in the data state to see if the first bit is a valid start bit or
of the transmitter is shown in figure 3 and the data frame not. It is a legitimate start bit if the bit is zero; otherwise,
is shown in figure 4. it is invalid. Inc sample counter (samples) will be asserted
based on the sampled values, which will increment the
value of the counter. To clear the counter, it asserts clr
sample counter. If the next three data in samples are all
zero, the machine determines that the start bit is valid and
switches to receiving mode. In the data state, 8 samples
for 8 data bits are taken. In this case, an inc sample
counter will be asserted. After that, the bit counter is
increased. When bit counter count values equal to no of
data samples then it changes state to stop state and in the
stop state, it samples completely the stop bit then switches
state to start state again. Figure 5 shows the state diagram
Fig. 3. State Diagram of Transmitter of the receiver. Figure 6 shows the schematic diagram of
UART.
Fig. 5. State Diagram of Receiver

Fig. 7. Simulation results of UART in ModelSim Altera

Fig. 6. Schematic diagram of UART

III. VERIFICATION METHODOLOGY

The complexity of verification is growing in tandem with
the rapid advancement of IC design. Verification is seen as a
distinct process from design, which has resulted in significant
advancements in the verification field. A verification environ-
ment (Test-bench) based on Verilog is built, which improves
verification efficiency and minimizes complexity.
Thus we wrote a test-bench file to reduce complexity in the
verification of the module. The test-bench applies a predeter-
mined sequence to the design and compares the results. The
Randomize functionality is used to produce random test cases
that will verify all of the functions’ hard-to-reach corner cases. Fig. 8. Simulation results of UART in ModelSim Altera
Random testing is more effective than other methods since
it provides tests for confirming the design automatically.
is used, which decreases the difficulty of developing the code.
IV. RESULTS
Randomization is used in the verification to verify the corner
The UART module is constructed and tested by compiling cases, and the assertion is used to shorten the verification time.
and simulating it in a test-bench created with Verilog. Figure Modelsim Altera software is used to simulate the design. The
7 and figure 8 show the simulation results of UART in Model- simulation findings are dependable and stable, according to
Sim Altera. the simulation results.
V. C ONCLUSION
R EFERENCES
Verilog is used to properly design and verify a half-duplex
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