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CMOS Analog VLSI Design Homework

This document provides instructions for homework assignment 1 on CMOS analog VLSI design. It consists of 3 questions involving SPICE simulations of MOSFET circuits. Question 1 involves extracting transistor parameters from a test setup and comparing results for different geometries. Question 2 involves plotting ID-VG and ID-VD characteristics for a MOSFET. Question 3 involves designing a common source amplifier to meet gain and bandwidth specifications and performing DC, transient, and AC analyses to verify the design meets specifications. The homework is due on August 16th 2019 and must follow specific formatting and submission guidelines.

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Raja Ram
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108 views2 pages

CMOS Analog VLSI Design Homework

This document provides instructions for homework assignment 1 on CMOS analog VLSI design. It consists of 3 questions involving SPICE simulations of MOSFET circuits. Question 1 involves extracting transistor parameters from a test setup and comparing results for different geometries. Question 2 involves plotting ID-VG and ID-VD characteristics for a MOSFET. Question 3 involves designing a common source amplifier to meet gain and bandwidth specifications and performing DC, transient, and AC analyses to verify the design meets specifications. The homework is due on August 16th 2019 and must follow specific formatting and submission guidelines.

Uploaded by

Raja Ram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE618 (Zele)

CMOS Analog VLSI Design : Homework - 1 [30 - Marks]


Submission Deadline : 16th Aug 2019 11:55 AM

• All problems are based on Cadence simulations


• The submission must contain appropriate plots labelled clearly.
• The submission must contain the theoretical calculations wherever it is applicable.
• Submission must be in Teamname Rollnumber Yourname Assignment1.pdf format.
• Submissions after deadline with not be accepted under any circumstances
• All MOSFET models should be used from SCL 180 nm library.
• MOSFETS in schematics must be annotated with all required parameters. Ex: Width, Length, Fingers, Multipliers.
• Report all values preferably in tabular format wherever it is appropriate.

Intent of this homework is to introduce you to various features of the tool used in circuit design.

Question 1 [10 Marks]


For the PMOS transistor test setup shown in Fig. 1 -

a). Assuming that VSG and VSD can take only two values i.e., either 0.6 V or 1.5 V, report the following transistor
parameters for W = 1.8 µm and L = 0.18 µm. [4 Marks]
b). Increase the length of the device by a factor of 10 keeping W/L constant and repeat part (a). [4 Marks]
c). Compare and explain the results obtained in Part (a) and (b). [2 Marks]

Parameter |Vgs | |Vds | Value (with appropritate units)


Vth (Linear)
Vth (Sat.)
β (Sat.)
Rout
gm ( |Vgs | = 0.6 V, |Vds | = 1.5 V)
gm ( |Vgs | = 0.6 V, |Vds | = 0.6 V)

Figure 1: Transistor parameters

Question 2 [10 Marks]


For the PMOS shown in Fig. 1, set W = 1.8 µm and L = 0.18 µm

a). Plot Id vs. |Vgs |, for |Vds | varying from 0 V to 1.8 V in 6 equal steps. Overlay all of them in one single plot.
[5 Marks]
b). Plot Id vs. |Vds |, for |Vgs | varying from 0 V to 1.8 V in 6 equal steps. Overlay all of them in one single plot.
[5 Marks]

Hint : For variable on X axis use DC sweep from 0 V to 1.8 V. For varying a parameter value use parametric analysis.

1
VDD

VIN
IB

VO

RD
CL

Figure 2: CS amplifier with resistive load

Question 3 [10 Marks]


For the Common source amplifier with resistive load shown in the Fig. 2, derive the gain and bandwidth equations.
Design the amplifier to obtain a gain ≥ 10 dB. Given VDD = 1.8 V, VIN = 0.9 V, VO = 0.9 V, CL = 1pF , IB = 100 µA,
L= 0.18 µm and finger width = 1 µm.
Note: Use resistor (res) from analogLib.

a). Show the step by step design procedure. Mention the number of fingers needed to meet the specifications.
[3 Marks]
b). Perform a dc operating point analysis and annotate the voltages at each node. [1 Marks]

c). Perform a transient analysis with a 10 mV sinusoidal input at 10 KHz. Plot the input and the output waveforms
and clearly mark the peak values. [2 Marks]
d). Perform ac analysis and clearly indicate (through markers/cursors) the dc gain and the bandwidth in the bode
plot. [2 Marks]
e). Tabulate the theoretical and simulated gain and bandwidth values. [2 Marks]

Theoretical Simulated
Gain (dB)
Bandwidth (Hz)

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