1. Verilog is based on C, while VHDL is based on Pascal and Ada.

2. Unlike Verilog, VHDL is strongly typed.

3. Ulike VHDL, Verilog is case sensitive.
4. Verilog is easier to learn compared to VHDL.
5. Verilog has very simple data types, while VHDL allows users to create more complex data
types.
6. Verilog lacks the library management, like that of VHDL

VHDL/Verilog compared & contrasted
This section compares and contrasts individual aspects of the two languages; they are listed in
alphabetical order.
Capability
Hardware structure can be modeled equally effectively in both VHDL and Verilog. When
modeling abstract hardware, the capability of VHDL can sometimes only be achieved in Verilog
when using the PLI. The choice of which to use is not therefore based solely on technical
capability but on:
personal preferences
EDA tool availability
commercial, business and marketing issues
The modeling constructs of VHDL and Verilog cover a slightly different spectrum across the
levels of behavioral abstraction; see Figure 1.

Figure 1. HDL modeling capability
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may
be separately compiled if so desired. However, it is good design practice to keep each design unit
in it's own system file in which case separate compilation should not be an issue.
Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a
means of speeding up simulation, but has not changed the original nature of the language. As a
result care must be taken with both the compilation order of code written in a single file and the
compilation order of multiple files. Simulation results can change by simply changing the order
of compilation.
Data types
VHDL. A multitude of language or user defined data types can be used. This may m ean
dedicated conversion functions are needed to convert objects from one type to another. The
choice of which data types to use should be considered wisely, especially enumerated (abstract)
data types. This will make models easier to write, clearer to read and avoid unnecessary
conversion functions that can clutter the code. VHDL may be preferred because it allows a
multitude of language or user defined data types to be used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much
geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike
VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the
user. There are net data types, for example wire, and a register data type called reg. A model with
a signal whose type is one of the net data types has a corresponding electrical wire in the implied
modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles
and should not be confused with the modeling of a hardware register. Verilog may be preferred
because of it's simplicity.
Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail able to any
design-unit that wishes to use them.
Verilog. There is no concept of packages in Verilog. Functions and procedures used within a
model must be defined in the module. To make functions and procedures generally accessible
from different module statements the functions and procedures must be placed in a separate
system file and included using the `include compiler directive.
Easiest to Learn
Starting with zero knowledge of either language, Verilog is probably the easiest to grasp and
understand. This assumes the Verilog compiler directive language for simulation and the PLI
language is not included. If these languages are included they can be looked upon as two
additional languages that need to be learned. VHDL may seem less intuitive at first for two
primary reasons. First, it is very strongly typed; a feature that makes it robust and powerful for
the advanced user after a longer learning phase. Second, there are many ways to model the same
circuit, specially those with large hierarchical structures.
Forward and back annotation
A spin-off from Verilog is the Standard Delay Format (SDF). This is a general purpose format
used to define the timing delays in a circuit. The format provides a bidirectional link between,
chip layout tools, and either synthesis or simulation tools, in order to provide more accurate
timing representations. The SDF format is now an industry standard in it's own right.
High level constructs
VHDL. There are more constructs and features for high-level modeling in VHDL than there are
in Verilog. Abstract data types can be used along with the following statements:
* package statements for model reuse,
* configuration statements for configuring design structure,
* generate statements for replicating structure,
* generic statements for generic models that can be individually characterized, for example, bit
width.
All these language statements are useful in synthesizable models.
Verilog. Except for being able to parameterize models by overloading parameter constants, there
is no equivalent to the high-level VHDL modeling statements in Verilog.
Language Extensions
The use of language extensions will make a model non standard and most likely not portable
across other design tools. However, sometimes they are necessary in order to achieve the desired
results.
VHDL. Has an attribute called 'foreign that allows architectures and subprograms to be modeled
in another language.
Verilog. The Programming Language Interface (PLI) is an interface mechanism between Verilog
models and Verilog software tools. For example, a designer, or more likely, a Verilog tool
vendor, can specify user defined tasks or functions in the C programming language, and then call
them from the Verilog source description. Use of such tasks or functions make a Verilog model
nonstandard and so may not be usable by other Verilog tools. Their use is not recommended.
Libraries
VHDL. A library is a store for compiled entities, architectures, packages and configurations.
Useful for managing multiple design projects.
Verilog. There is no concept of a library in Verilog. This is due to it's origins as an interpretive
language.
Low Level Constructs
VHDL. Simple two input logical operators are built into the language, they are: NOT, AND, OR,
NAND, NOR, XOR and XNOR. Any timing must be separately specified using the after clause.
Separate constructs defined under the VITAL language must be used to define the cell primitives
of ASIC and FPGA libraries.
Verilog. The Verilog language was originally developed with gate level modeling in mind, and
so has very good constructs for modeling at this level and for modeling the cell primitives of
ASIC and FPGA libraries. Examples include User Defined Primitive s (UDP), truth tables and
the specify block for specifying timing delays across a module.
Managing large designs
VHDL. Configuration, generate, generic and package statements all help manage large design
structures.
Verilog. There are no statements in Verilog that help manage large designs.
Operators
The majority of operators are the same between the two languages. Verilog does have very
useful unary reduction operators that are not in VHDL. A loop statement can be used in VHDL
to perform the same operation as a Verilog unary reduction operator. VHDL has the mod
operator that is not found in Verilog.
Parameterizable models
VHDL. A specific bit width model can be instantiated from a generic n-bit model using the
generic statement. The generic model will not synthesize until it is instantiated and the value of
the generic given.
Verilog. A specific width model can be instantiated from a generic n-bit model using overloaded
parameter values. The generic model must have a default parameter value defined. This means
two things. In the absence of an overloaded value being specified, it will still synthesize, but will
use the specified default parameter value. Also, it does not need to be instantiated with an
overloaded parameter value specified, before it will synthesize.
Procedures and tasks
VHDL allows concurrent procedure calls; Verilog does not allow concurrent task calls.
Readability
This is more a matter of coding style and experience than language feature. VHDL is a concise
and verbose language; its roots are based on Ada. Verilog is more like C because it's constructs
are based approximately 50% on C and 50% on Ada. For this reason an existing C programmer
may prefer Verilog over VHDL. Although an existing programmer of both C and Ada may find
the mix of constructs somewhat confusing at first. Whatever HDL is used, when writing or
reading an HDL model to be synthesized it is important to think about hardware intent.
Structural replication
VHDL. The generate statement replicates a number of instances of the same design-unit or some
sub part of a design, and connects it appropriately.
Verilog. There is no equivalent to the generate statement in Verilog.
Test harnesses
Designers typically spend about 50% of their time writing synthesizable models and the other
50% writing a test harness to verify the synthesizable models. Test harnesses are not restricted to
the synthesizable subset and so are free to use the full potential of the language. VHDL has
generic and configuration statements that are useful in test harnesses, that are not found in
Verilog.
Verboseness
VHDL. Because VHDL is a very strongly typed language models must be coded precisely with
defined and matching data types. This may be considered an advantage or disadvantage.
However, it does mean models are often more verbose, and the code often longer, than it's
Verilog equivalent.
Verilog. Signals representing objects of different bits widths may be assigned to each other. The
signal representing the smaller number of bits is automatically padded out to that of the larger
number of bits, and is independent of whether it is the assigned signal or not. Unused bits will be
automatically optimized away during the synthesis process. This has the advantage of not
needing to model quite so explicitly as in VHDL, but does mean unintended modeling errors will
not be identified by an analyzer.