Exceptions
Exceptions generated as the direct effect of executing an instruction
Software Interrupts, Undefined Instructions & Prefetch Aborts
Exceptions generated as a side effect of an Instruction
Data Aborts (Caused by Load/Store Instructions)
Exceptions generated externally, unrelated to Instruction flow
Reset, IRQ, FIQ
ARM Exceptions
Vector 0x0 0x4 0x8 0xC 0x10 0x18 0x1C Exception Reset Undefined Instruction Software Interrupt Prefetch Abort Data Abort IRQ FIQ Mode Supervisor Undef Supervisor Abort Abort IRQ FIQ Priority 1 6 6 5 2 4 3
0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C
Reset Undefined Instruction Software Interrupt Prefetch Abort Data Abort Reserved IRQ FIQ
ARM Exceptions (2)
Each entry in the vector table is 32 bits(1 word). The vector table contains a branch instruction or a load PC instruction to the appropriate handler. Each mode has its own subset of banked registers.
R13 Stack Pointer R14 Link Register SPSR Saved Program Status Register.
Each handler must ensure that the other registers are restored to their original contents upon exit.
Register Example: User to FIQ Mode
Registers in use
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq
Registers in use
User Mode
FIQ Mode
r0 r1 r2 r3 r4 r5 r6
EXCEPTION
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)
r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) cpsr spsr_fiq
Return address calculated from User mode PC value and stored in FIQ mode LR
spsr_fiq
User mode CPSR copied to FIQ mode SPSR
Disable FIQ
Exception Entry
Changes Operating Mode Save Address of next Instruction in r14 of the new mode Saves Old value of CPSR into SPSR of new mode Disables either IRQ or FIQ if the exception is IRQ or FIQ respectively Forces PC to vector to new address
Exception Return
Any modified user registers should be restored from the Stack The CPSR should be restored from appropriate SPSR The PC must be changed to relevant User Instruction Stream
Problem: Last two cannot be carried out independently.
Solution
To return from SWI
MOVS pc, r14
To return from IRQ, FIQ or Prefetch Abort
SUBS pc, r14, #4
To return from Data Aborts
SUBS pc, r14, #8
The S modifier signifies special form of Instruction when the destination is PC This way only if SPSR, r14 stored onto the Stack: LDMFD r13!, {r0-r3,pc} ^
Software Interrupt (SWI)
LDR r0, [lr, #-4] BIC r0, r0, #0xFF000000 BL service_routine MOVS pc, lr ; this will load r0 with ; the actual swi instruction ; r0 will now contain the ; swi number ; Call the service_routine for the swi ; number ; Return from SWI Handler
BackUp
Response to an exception
Exception generated Copy the CPSR of old mode into the SPSR of the current mode Change mode bits of CPSR to the appropriate mode and map in the appropriate banked registers. Change CPSR to disable interrupts (IRQ or FIQ if required) Copy (PC 4) to link register of the exception mode Change Program counter to the appropriate interrupt vector, which forces a branch
Return from an exception handler
Involves the following Restore the CPSR from the SPSR of the interrupt mode Restore the program counter from the link register For simple returns that do not require restoration from stack these two can be done by performing a data processing instruction with The S flag set The program counter as destination For example
MOVS R15, R14
For exception handlers that uses the stack return is done using LDMFD sp! , {r0-r12,pc} ^
