Scribd
Upload
227 views1 page

VHDL Code For Adder

This VHDL code defines an n-bit adder with a generic parameter n. The adder takes in two n-bit inputs A and B, and outputs an n-bit sum and a 1-bit carry. It defines the entity and architecture, including ports and a signal to store the result. The result is computed by concatenating A and B with 0's and adding them, with the highest bit assigned to the carry output and the lower n bits to the sum output.

Uploaded by

mnpaliwal020
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
227 views1 page

VHDL Code For Adder

This VHDL code defines an n-bit adder with a generic parameter n. The adder takes in two n-bit inputs A and B, and outputs an n-bit sum and a 1-bit carry. It defines the entity and architecture, including ports and a signal to store the result. The result is computed by concatenating A and B with 0's and adding them, with the highest bit assigned to the carry output and the lower n bits to the sum output.

Uploaded by

mnpaliwal020
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 1

--------------------------------------------------------

-- VHDL code for n-bit adder (ESD figure 2.5)


-- by Weujun Zhang, 04/2001
--
-- function of adder:
-- A plus B to get n-bit sum and 1 bit carry
-- we may use generic statement to set the parameter
-- n of the adder.
--------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------

entity ADDER is

generic(n: natural :=2);


port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);

end ADDER;

--------------------------------------------------------

architecture behv of ADDER is

-- define a temparary signal to store the result

signal result: std_logic_vector(n downto 0);

begin

-- the 3rd bit should be carry

result <= ('0' & A)+('0' & B);


sum <= result(n-1 downto 0);
carry <= result(n);

end behv;

--------------------------------------------------------

You might also like