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ECE590 - Tutorial 6 (UiTM)

This document contains 10 questions about digital logic circuits and flip-flops. The questions ask the reader to determine output waveforms for various flip-flop configurations, design counters to produce specific sequences, and analyze counter circuits. Diagrams and figures are provided to illustrate the circuit configurations being asked about.

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402 views3 pages

ECE590 - Tutorial 6 (UiTM)

This document contains 10 questions about digital logic circuits and flip-flops. The questions ask the reader to determine output waveforms for various flip-flop configurations, design counters to produce specific sequences, and analyze counter circuits. Diagrams and figures are provided to illustrate the circuit configurations being asked about.

Uploaded by

Nazhammerheart
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 590

Tut#6 (Digital Logic Circuits)

Question 1

For a positive edge-triggered J-K flip-flop with inputs as shown in Figure 8-81,
determine the Q output relative to the clock. Assume that Q starts LOW.

Question 2

Determine the Q waveform relative to the clock if the signals shown in Figure 8-83 are
applied to the inputs of the J-K flip-flop. Assume that Q is initially low.

1
Question 3

For a negative edge-triggered J-K flip-flop with the inputs in Figure 8-84, develop the
Q output waveform relative to the clock. Assume that Q is initially LOW.

Question 4
For the ripple counter in Figure 9-70, show the complete timing diagram for 8th clock
pulses. Show the clock. Q0, Q1, and Q2 waveforms.

Question 5

Determine the sequence of the counter in Figure 9-77.

Figure 9-77
2
Question 6

Design a counter to produce the following sequence. Use J-K flip-flops.

00, 10, 01, 11, 00, ...

Question 7

Design a counter to produce the following binary sequence. Use J-K flip-flops.

1, 4, 3, 5, 7, 6, 2, 1, ...

Question 8

Design a synchronous counter that produces the following sequence: 4, 5, 2, 6, 0


using JK flip-flop(s).

Question 9

Draw a circuit for an asynchronous counter using negative trigger JK flip-flop(s) that
produces the following sequence: 7, 6, 2, 1, 0

Question 10

Analyze the asynchronous counter circuit of Figure Q4(c) below. All JK and SET inputs
are connected to logic "1". Hence :-

i) determine the counting sequence


ii) sketch the waveforms of QA, QB and QC up to 5 clock pulses.

Figure Q4(c)

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