Something We Cant Build (Yet)
What if you were given the following design specification:
When the button is pushed: 1) Turn on the light if it is off 2) Turn off the light if it is on The light should change state within a second of the button press
button
light
What makes this circuit so different from those weve discussed before? 1. State i.e. the circuit has memory 2. The output was changed by a input event (pushing a button) rather than an input value
6.111 Fall 2007 Lecture 5, Slide 1
One model of what wed like to build
Digital State
New State
Memory Device
LOAD Input
Current State
Combinational Logic
Output
Plan: Build a Sequential Circuit with stored digital STATE Memory stores CURRENT state, produced at output
Combinational Logic computes NEXT state (from input, current state) OUTPUT bit (from input, current state) State changes on LOAD control input
6.111 Fall 2007 Lecture 5, Slide 2
Storage: Using Feedback
IDEA: use positive feedback to maintain storage indenitely. Our logic gates are built to restore marginal signal levels, so noise shouldnt be a problem! Result: a bistable storage element
VIN
VTC for inverter pair Feedback constraint: VIN = VOUT
VOUT Not aected by noise
VOUT
Three solutions: two end-points are stable middle point is unstable
VIN Well get back to this!
Lecture 5, Slide 3
6.111 Fall 2007
Settable Storage Element
Its easy to build a se able storage element (called a latch) using a lenient MUX: Heres a feedback path,
so its no longer a combinational circuit.
state signal appears as both input and output
G D QIN QOUT Y Q 0 0 1 1 --0 1 0 1 --0 1 0 1
Q stable Q follows D
D B S G
6.111 Fall 2007
Lecture 5, Slide 4
New Device: D Latch
G=1: Q follows D Q A D G
D G Q
TPD TPD BUT A change in D or G contaminates Q, hence Q how can this possibly work? 0 1
G=0: Q holds
V2
Q Y
D G Q
V1
V1
V2
G=1: Q Follows D, independently of Q G=0: Q Holds stable Q, independently of D
6.111 Fall 2007
Lecture 5, Slide 5
D-Latch timing
D Stable
Q A D G
0 1
Q Y
D G Q
V2
V2 TPD TPD TPD
To reliably latch V2:
Apply V2 to D, holding G=1 After TPD, V2 appears at Q=Q After another TPD, Q & D both valid for TPD; will hold Q=V2 independently of G Set G=0, while Q & D hold Q=D After another TPD, G=0 and Q are sucient to hold Q=V2 independently of D
6.111 Fall 2007
TSETUP THOLD
Dynamic Discipline for our latch:
TSETUP = 2TPD: interval prior to G transition for which D must be stable & valid THOLD = TPD: interval following G transition for which D must be stable & valid
Lecture 5, Slide 6
NOR-based Set-Reset (SR) Flipflop
S S S R Q Q R Q Q 0 1 0 1 R 0 0 1 1 Q Q 1 0 0 Q Q 0 1 0
Forbidden State
Reset R S Q Q Hold Set Reset Set
??
Flip-flop refers to a bi-stable element
6.111 Fall 2007
Lecture 5, Slide 7
Lets try using the D-Latch
New State
D G
Input
Q
Current State
Combinational Logic
Output
Plan: Build a Sequential Circuit with one bit of STATE Single latch holds CURRENT state
Combinational Logic computes NEXT state (from input, current state) OUTPUT bit (from input, current state) State changes when G = 1 (briey!)
6.111 Fall 2007 Lecture 5, Slide 8
What happens when G=1?
Combinational Cycles
New State
Q
Current State
1
Input
Combinational Logic
Output
When G=1, latch is Transparent
provides a combinational path from D to Q. Cant work without tricky timing constrants on G=1 pulse: Must t within contamination delay of logic Must accommodate latch setup, hold times
6.111 Fall 2007
Looks like a stupid Approach to me
Want to signal an INSTANT, not an INTERVAL
Lecture 5, Slide 9
Edge-triggered D-Register
The gate of this latch is open when the clock is low
D
D0 0 1 1
S
D G
D G
D CLK
What does that one do?
master
slave
The gate of this latch is open when the clock is high
CLK
Observations: only one latch transparent at any time: Transitions mark instants, not intervals master closed when slave is open slave closed when master is open no combinational path through ip op
(the feedback path in one of the master or slave latches is always active)
Q only changes shortly after 0 1 transition of CLK, so ip op appears to be triggered by rising edge of CLK
6.111 Fall 2007 Lecture 5, Slide 10
D-Register Waveforms
D D G CLK Q D G Q Q D CLK D Q Q
master
slave
D CLK
Q
master closed slave open
6.111 Fall 2007
slave closed master open
Lecture 5, Slide 11
D-Register Timing - I
Values determined from slave latch
<tPD
D CLK
D Q
>tCD
Q CLK D
tPD: maximum propagation delay, CLK Q tCD: minimum contamination delay, CLK Q tSETUP: setup time tHOLD: hold time
6.111 Fall 2007
>tSETUP >tHOLD
Values determined from master latch
guarantee that D has propagated through feedback path before master closes guarantee master is closed and data is stable before allowing D to change
Lecture 5, Slide 12
D-Register Timing - II
Questions for register-based designs:
D Q
reg1
CLK
reg2
how much time for useful work (i.e. for combinational logic delay)? does it help to guarantee a minimum tCD? How about designing registers so that tCD,reg > tHOLD,reg?
t1 CLK
t2
what happens if CLK signal doesnt arrive at the two registers at exactly the same t1 = tCD,reg1 + tCD,1 > tHOLD,reg2 time (a phenomenon known as t2 = tPD,reg1 + tPD,1 < tCLK - tSETUP,reg2 clock skew)?
6.111 Fall 2007 Lecture 5, Slide 13
Sequential Circuit Timing
tCD,R = 1ns tPD,R = 3ns tS,R = 2ns Current tH,R = 2ns State Clock Input New State
Combinational Logic
tCD,L = ? tPD,L = 5ns
Output
Questions:
Constraints on TCD for the logic? Minimum clock period? Setup, Hold times for Inputs?
> 1 ns > 10 ns (TPD,R+TPD,L+ TS,R) TS = TPD,L +TS,R TH = TH,R -TCD,L
This is a simple Finite State Machine more on next time!
6.111 Fall 2007 Lecture 5, Slide 14
The Sequential always Block
Edge-triggered circuits are described using a sequential always block
Combinational
module combinational(a, b, sel, out); input a, b; input sel; output out; reg out; always @ (a or b or sel) begin if (sel) out = a; else out = b; end endmodule
Sequential
module sequential(a, b, sel, clk, out); input a, b; input sel, clk; output out; reg out; always @ (posedge clk) begin if (sel) out <= a; else out <= b; end endmodule
a b
1 out 0 sel
a b
1 D Q 0 sel clk
Lecture 5, Slide 15
out
6.111 Fall 2007
Importance of the Sensitivity List
The use of posedge and negedge makes an always block sequential (edge-triggered) Unlike a combinational always block, the sensitivity list does determine behavior for synthesis!
D Flip-flop with synchronous clear
module dff_sync_clear(d, clearb, clock, q); input d, clearb, clock; output q; reg q; always @ (posedge clock) begin if (!clearb) q <= 1'b0; else q <= d; end endmodule
D Flip-flop with asynchronous clear
module dff_async_clear(d, clearb, clock, q); input d, clearb, clock; output q; reg q; always @ (negedge clearb or posedge clock) begin if (!clearb) q <= 1b0; else q <= d; end endmodule
always block entered only at each positive clock edge
always block entered immediately when (active-low) clearb is asserted
Note: The following is incorrect syntax: always @ (clear or negedge clock) If one signal in the sensitivity list uses posedge/negedge, then all signals must.
Assign any signal or variable from only one always block, Be wary of race conditions: always blocks execute in parallel
6.111 Fall 2007 Lecture 5, Slide 16
Blocking vs. Nonblocking Assignments
Verilog supports two types of assignments within always blocks, with subtly different behaviors. Blocking assignment: evaluation and assignment are immediate
always @ (a or b or c) begin x = a | b; y = a ^ b ^ c; z = b & ~c; end 1. Evaluate a | b, assign result to x 2. Evaluate a^b^c, assign result to y 3. Evaluate b&(~c), assign result to z
Nonblocking assignment: all assignments deferred until all righthand sides have been evaluated (end of simulation timestep)
always begin x <= y <= z <= end @ (a or b or c) a | b; a ^ b ^ c; b & ~c; 1. Evaluate a | b but defer assignment of x 2. Evaluate a^b^c but defer assignment of y 3. Evaluate b&(~c) but defer assignment of z 4. Assign x, y, and z with their new values
Sometimes, as above, both produce the same result. Sometimes, not!
Lecture 5, Slide 17
6.111 Fall 2007
Assignment Styles for Sequential Logic
Flip-Flop Based Digital Delay Line
in clk D Q q1 D Q q2 D Q out
Will nonblocking and blocking assignments both produce the desired result?
module nonblocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end endmodule module blocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end endmodule
6.111 Fall 2007
Lecture 5, Slide 18
Use Nonblocking for Sequential Logic
always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end At each rising clock edge, q1, q2, and out simultaneously receive the old values of in, q1, and q2. always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end At each rising clock edge, q1 = in. After that, q2 = q1 = in. After that, out = q2 = q1 = in. Therefore out = in. q1 q2 D Q
q1 in clk D Q D Q
q2 D Q out clk in
out
Guideline: use nonblocking assignments for sequential always blocks
6.111 Fall 2007
Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logic
Lecture 5, Slide 19
Use Blocking for Combinational Logic
Blocking Behavior
(Given) Initial Condition a changes; always block triggered
abc xy 110 010 010 010 11 11 01 00
a b c x y
module blocking(a,b,c,x,y); input a,b,c; output x,y; reg x,y; always @ (a or b or c) begin x = a & b; y = x | c; end endmodule
x = a & b; y = x | c;
Nonblocking Behavior
(Given) Initial Condition a changes; always block triggered
abc xy 110 010 010 010 010 11 11 11 11 01
Deferred
module nonblocking(a,b,c,x,y); input a,b,c; output x,y; reg x,y; always @ (a or b or c) begin x <= a & b; y <= x | c; end endmodule
x <= a & b; y <= x | c;
Assignment completion
x<=0 x<=0, y<=1
6.111 Fall 2007
Guideline: use blocking assignments for combinational always blocks
Nonblocking and blocking assignments will synthesize correctly. Will both styles simulate correctly? Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic While nonblocking assignments can be hacked to simulate correctly (expand the sensitivity list), its not elegant
Lecture 5, Slide 20
Implementation for on/off button
button light module onoff(button,light); input button; output light; reg light; always @ (posedge button) begin light <= ~light; end BUTTON endmodule
6.111 Fall 2007
D Q Q
LIGHT
Lecture 5, Slide 21
A Simple Counter
Isn t this a lot like Exercise 1 in Lab 2?
+1
0 1 0 enb
1 4 0 clr clk
count
# 4-bit counter with enable and synchronous clear module counter(clk,enb,clr,count); input clk,enb,clr; output [3:0] count; reg [3:0] count; always @ (posedge clk) begin count <= clr ? 4b0 : (enb ? count+1 : count); end endmodule
6.111 Fall 2007 Lecture 5, Slide 22
