testing with different circuit

Author: xinoip

SupplementaryMaterials/false_path.v

@@ -0,0 +1,20 @@
+// Verilog
+// false_path
+// Ninputs 3
+// Noutputs 1
+// NtotalGates 2
+// NAND2 1
+// OR2 1
+
+module falsepath (A,B,G);
+
+input A,B;
+
+output G;
+
+wire F;
+
+nand NAND2_1 (F, A, B);
+nor OR2_1 (G, F, B);
+
+endmodule

currentcircuit.cpp

@@ -121,7 +121,12 @@ void CurrentCircuit::topological_sort() {
  atpg_element.name = element.elementName;
  //TODO: only NAND for testing
  if(element.isGate()) {
- atpg_element.type = ATPGCircuitElementType::NAND;
+ if(element.elementType == CircuitElementType::NAND) {
+ atpg_element.type = ATPGCircuitElementType::NAND;
+ }
+ if(element.elementType == CircuitElementType::NOR) {
+ atpg_element.type = ATPGCircuitElementType::NOR;
+ }
  } else {
  atpg_element.type = ATPGCircuitElementType::WIRE;
  }