Hi! Is there any direct support or equivalence for the bit-replicate operator in PyMTL? I am trying to implement some logic like this:

// Verilog logic [2:0] A; logic [NBITS-1 : 0] B; B = { NBITS{ A[1] }}; 

I searched for several related keywords in the repository but did not find useful information.

Also, I have tried the updates in Improving concat #278. However, such generator expression is still rejected inside the update/update_ff block.

# PyMTL # - invalid operation: generator expression # code-1 s.B //= lambda: concat( s.A[1] for _ in range(NBITS) ) # code-2 @update def bit_replicate(): s.B @= concat( s.A[1] for _ in range(NBITS) ) 

Update: Okay I think the sext() is a workaround for 1 bit :) Then what if there are multiple bits to be replicated?