RFSoC4x2 (ZU48DR) R2C (real to complex) Runtime Tuning: Q-Channel Amplitude Halved after Frequency Change (PetaLinux 2024.1)

RFSoC DAC and ADC AXIS Data Sample Format

Debug information is missing in fsbl despite being enabled

lwip udp perf server in Vitis 2025.2 stuck in loop: while (((netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))

Building PMUFW with eFuse flags generates PMU_RAM overflowed by n bytes using Yocto tools. What may I disable to generate PMU_RAM with correct size?

Hi, I'm faced to the same problem as described here: https://adaptivesupport.amd.com/s/article/67132?language=en_US In my flow, doing 'setenv...

Debugging with multiple ZCU eval boards - how to direct GDB / hw_server?

Vitis 2025.2 - Cant create platform with FreeRTOS as OS

Vivado/Vitis 2024.1.1 An internal exception error.

Clock wizard generated clocks are not recognised by devicetree generator

How to implement a YOLO model on an FPGA/MPSoC

Clarification on DMA options in Zynq UltraScale+ MPSoC PCIe Root Complex mode

The QDMA bridge_s_axi interface does not return bvalid response after the 16th transaction

VPK120开发板，petalinux生成固件进入uboot无法访问flash

I am using an UltraScale+ MPSoC and working with the PCI Express Controller IP.