ALU 설계 - data processor

Author: minji-o-j

lab_07/lab_7_data_processor.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY lab_7_data_processor IS
+ PORT (	clk:INSTD_LOGIC;
+input:INSTD_LOGIC_VECTOR(3 DOWNTO 0);
+input_sel:INSTD_LOGIC;
+ac_load:INSTD_LOGIC;
+alu_sel:INSTD_LOGIC_VECTOR(2 DOWNTO 0);
+mar_in:INSTD_LOGIC_VECTOR(2 DOWNTO 0);
+mar_load:INSTD_LOGIC;
+ram_load:INSTD_LOGIC;
+mux_out_chk:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0);
+output:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0);--ac out
+data_chk:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0);--alu out
+mar_out_chk:OUTSTD_LOGIC_VECTOR(2 DOWNTO 0);
+m1_out:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0);--ram out
+m2_out:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0)--ram out2
+);
+END lab_7_data_processor;
+----------------------------------------------------------------
+ARCHITECTURE structual OF lab_7_data_processor IS
+SIGNAL ac	:STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL mux_out	:STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL mar	:STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL ram_out	:STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL alu_out	:STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+
+----------------------------------------------------------------
+COMPONENT lab_7_asyncRAM
+PORT (	data_in: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+address: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+wr: IN STD_LOGIC;
+data_out:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+m1_out:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0);
+m2_out:OUTSTD_LOGIC_VECTOR(3 DOWNTO 0));
+END COMPONENT;
+
+COMPONENT lab_7_simple_alu
+PORT (	op1, op2 : INSTD_LOGIC_VECTOR (3 DOWNTO 0);
+sel:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+alu_out: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
+END COMPONENT;
+----------------------------------------------------------------
+BEGIN
+RAM:	lab_7_asyncRAMPORT MAP(data_in=>alu_out,address=>mar,wr=>ram_load,data_out=>ram_out,m1_out=>m1_out,m2_out=>m2_out);
+ALU:	lab_7_simple_aluPORT MAP(op1=>ac,op2=>ram_out,sel=>alu_sel,alu_out=>alu_out);
+----------------------------------------------------------------
+--MUX
+mux_out<=input WHEN input_sel='1' ELSE alu_out;
+----------------------------------------------------------------
+--AC
+PROCESS(clk,ac_load)
+BEGIN
+IF clk'EVENT AND clk='1' THEN --load
+IF ac_load='1' THEN
+ac<=mux_out;
+END IF;
+END IF;
+END PROCESS;
+----------------------------------------------------------------
+--MAR
+PROCESS(clk,mar_load)
+BEGIN
+IF clk'EVENT AND clk='1' THEN --load
+IF mar_load='1' THEN
+mar<=mar_in;
+END IF;
+END IF;
+END PROCESS;
+----------------------------------------------------------------
+output<=ac;
+data_chk<=alu_out;
+mux_out_chk<=mux_out;
+mar_out_chk<=mar;
+END structual;

lab_07/lab_7_data_processor.vhd.bak

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