CU DP Design

Author: minji-o-j

lab_08/lab_8_2.vhd.bak

@@ -0,0 +1,56 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+Entity lab_8_2 is
+
+port(
+clk : IN STD_LOGIC ;
+load : IN STD_LOGIC ;
+clear : IN STD_LOGIC ;
+out_sel	: IN std_logic ;
+
+iNOT10	: out std_logic; --status signal
+dp_out	: out std_logic_vector(3 downto 0)--display out
+
+);
+
+END lab_8_2;
+
+Architecture dataflow of lab_8_2 is
+signal iNOT10S: std_logic :='1';
+signal data : std_logic_vector(3 downto 0) := "0000";
+TYPE state_type IS(S0,S1,S2,S3);
+SIGNAL state:state_type;
+
+begin
+
+process(clear, clk) is
+begin 
+
+if (clear = '1') then
+data <= "0000";
+state<=S0;
+
+elsif (clk'EVENT AND clk = '1') then
+if (load = '1' and iNOT10S/='0') then
+data <= data + '1';
+if(out_sel='1') then
+dp_out<=data;
+else
+dp_out <= "ZZZZ";
+end if;
+if data="1010" then
+iNOT10S<='0';
+end if;
+
+elsif (out_sel='0') then
+dp_out<="ZZZZ";
+end if;
+end if;
+end process;
+
+iNOT10<=iNOT10S;
+
+end dataflow;

lab_08/lab_8_2_nativelink_simulation.rpt

@@ -0,0 +1,22 @@
+Info: Start Nativelink Simulation process
+
+========= EDA Simulation Settings =====================
+
+Sim Mode : Gate
+Family : cycloneivgx
+Quartus root : c:/altera/13.1/quartus/bin64/
+Quartus sim root : c:/altera/13.1/quartus/eda/sim_lib
+Simulation Tool : modelsim-altera
+Simulation Language : vhdl
+Version : 93
+Simulation Mode : GUI
+Sim Output File : lab_8_2_6_1200mv_85c_slow.vho
+Sim SDF File : lab_8_2_6_1200mv_85c_vhd_slow.sdo
+Sim dir : simulation\modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim-Altera software
+Sourced NativeLink script c:/altera/13.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Warning: File lab_8_2_run_msim_gate_vhdl.do already exists - backing up current file as lab_8_2_run_msim_gate_vhdl.do.bak1
+Info: Spawning ModelSim-Altera Simulation software