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rom_example2
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‎lab_04/rom/rom_example2.vhd‎

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-- megafunction wizard: %ROM: 1-PORT%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altsyncram
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-- ============================================================
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-- File Name: rom_example2.vhd
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-- Megafunction Name(s):
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-- altsyncram
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY rom_example2 IS
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PORT
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(
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address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
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clock : IN STD_LOGIC := '1';
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q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
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);
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END rom_example2;
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ARCHITECTURE SYN OF rom_example2 IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
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BEGIN
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q <= sub_wire0(0 DOWNTO 0);
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altsyncram_component : altsyncram
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GENERIC MAP (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => "rom2.mif",
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intended_device_family => "Cyclone IV E",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 8,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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widthad_a => 3,
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width_a => 1,
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width_byteena_a => 1
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)
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PORT MAP (
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address_a => address,
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clock0 => clock,
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q_a => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: Clken NUMERIC "0"
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-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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-- Retrieval info: PRIVATE: MIFfilename STRING "rom2.mif"
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-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
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-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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-- Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
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-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
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-- Retrieval info: PRIVATE: rden NUMERIC "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: INIT_FILE STRING "rom2.mif"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
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-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
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-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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-- Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
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-- Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
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-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.inc TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.bsf TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2_inst.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2_syn.v TRUE
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-- Retrieval info: LIB_FILE: altera_mf

‎lab_04/rom/rom_example2_inst.vhd‎

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rom_example2_inst : rom_example2 PORT MAP (
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address => address_sig,
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clock => clock_sig,
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q => q_sig
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);

‎lab_04/rom/rom_example2_syn.v‎

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// megafunction wizard: %ROM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: rom_example2.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// ************************************************************
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20+
21+
//Copyright (C) 1991-2013 Altera Corporation
22+
//Your use of Altera Corporation's design tools, logic functions
23+
//and other software and tools, and its AMPP partner logic
24+
//functions, and any output files from any of the foregoing
25+
//(including device programming or simulation files), and any
26+
//associated documentation or information are expressly subject
27+
//to the terms and conditions of the Altera Program License
28+
//Subscription Agreement, Altera MegaCore Function License
29+
//Agreement, or other applicable license agreement, including,
30+
//without limitation, that your use is for the sole purpose of
31+
//programming logic devices manufactured by Altera and sold by
32+
//Altera or its authorized distributors. Please refer to the
33+
//applicable agreement for further details.
34+
35+
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//altsyncram ADDRESS_ACLR_A="NONE" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="rom2.mif" NUMWORDS_A=8 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=1 WIDTH_BYTEENA_A=1 WIDTHAD_A=3 address_a clock0 q_a
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//VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_decode 2013:10:23:18:05:48:SJ cbx_lpm_mux 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_stratixiii 2013:10:23:18:05:48:SJ cbx_stratixv 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = M9K 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
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module rom_example2_altsyncram
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(
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address_a,
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clock0,
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q_a) /* synthesis synthesis_clearbox=1 */;
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input [2:0] address_a;
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input clock0;
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output [0:0] q_a;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock0;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [0:0] wire_ram_block1a_0portadataout;
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wire [2:0] address_a_wire;
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cycloneive_ram_block ram_block1a_0
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(
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.clk0(clock0),
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.portaaddr({address_a_wire[2:0]}),
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.portadataout(wire_ram_block1a_0portadataout[0:0]),
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.portare(1'b1),
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.portbdataout()
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.clk1(1'b0),
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.clr0(1'b0),
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.clr1(1'b0),
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.ena0(1'b1),
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.ena1(1'b1),
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.ena2(1'b1),
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.ena3(1'b1),
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.portaaddrstall(1'b0),
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.portabyteenamasks({1{1'b1}}),
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.portadatain({1{1'b0}}),
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.portawe(1'b0),
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.portbaddr({1{1'b0}}),
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.portbaddrstall(1'b0),
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.portbbyteenamasks({1{1'b1}}),
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.portbdatain({1{1'b0}}),
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.portbre(1'b1),
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.portbwe(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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// synopsys translate_off
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,
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.devclrn(1'b1),
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.devpor(1'b1)
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// synopsys translate_on
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);
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defparam
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ram_block1a_0.clk0_core_clock_enable = "none",
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ram_block1a_0.clk0_input_clock_enable = "none",
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ram_block1a_0.connectivity_checking = "OFF",
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ram_block1a_0.init_file = "rom2.mif",
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ram_block1a_0.init_file_layout = "port_a",
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ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
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ram_block1a_0.mem_init0 = 8'h54,
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ram_block1a_0.operation_mode = "rom",
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ram_block1a_0.port_a_address_clear = "none",
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ram_block1a_0.port_a_address_width = 3,
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ram_block1a_0.port_a_data_out_clear = "none",
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ram_block1a_0.port_a_data_out_clock = "none",
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ram_block1a_0.port_a_data_width = 1,
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ram_block1a_0.port_a_first_address = 0,
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ram_block1a_0.port_a_first_bit_number = 0,
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ram_block1a_0.port_a_last_address = 7,
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ram_block1a_0.port_a_logical_ram_depth = 8,
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ram_block1a_0.port_a_logical_ram_width = 1,
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ram_block1a_0.ram_block_type = "AUTO",
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ram_block1a_0.lpm_type = "cycloneive_ram_block";
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assign
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address_a_wire = address_a,
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q_a = {wire_ram_block1a_0portadataout[0]};
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endmodule //rom_example2_altsyncram
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module rom_example2 (
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address,
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clock,
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q)/* synthesis synthesis_clearbox = 1 */;
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input[2:0] address;
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input clock;
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output[0:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [0:0] sub_wire0;
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wire [0:0] q = sub_wire0[0:0];
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rom_example2_altsyncramrom_example2_altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.q_a (sub_wire0));
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "rom2.mif"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
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// Retrieval info: PRIVATE: WidthData NUMERIC "1"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "rom2.mif"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
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// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.vhd TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.inc TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.cmp TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2_inst.vhd TRUE
217+
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_example2_syn.v TRUE
218+
// Retrieval info: LIB_FILE: altera_mf

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