rom_example

Author: minji-o-j

lab_04/rom/rom_example.qws

@@ -0,0 +1,144 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom_example.vhd
+-- Megafunction Name(s):
+--	altsyncram
+--
+-- Simulation Library Files(s):
+--	altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors. Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY rom_example IS
+PORT
+(
+address	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+clock	: IN STD_LOGIC := '1';
+q	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+);
+END rom_example;
+
+
+ARCHITECTURE SYN OF rom_example IS
+
+SIGNAL sub_wire0	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+BEGIN
+q <= sub_wire0(2 DOWNTO 0);
+
+altsyncram_component : altsyncram
+GENERIC MAP (
+address_aclr_a => "NONE",
+clock_enable_input_a => "BYPASS",
+clock_enable_output_a => "BYPASS",
+init_file => "rom1.mif",
+intended_device_family => "Cyclone IV E",
+lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+lpm_type => "altsyncram",
+numwords_a => 8,
+operation_mode => "ROM",
+outdata_aclr_a => "NONE",
+outdata_reg_a => "UNREGISTERED",
+widthad_a => 3,
+width_a => 3,
+width_byteena_a => 1
+)
+PORT MAP (
+address_a => address,
+clock0 => clock,
+q_a => sub_wire0
+);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "rom1.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "3"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "rom1.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example_inst.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_example_syn.v TRUE
+-- Retrieval info: LIB_FILE: altera_mf