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soc: arm: Introduce Infineon CAT1/PSoC 6 SOC integration
Add initial version of Infineon CAT1/PSoC 6 SOC integration. Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
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‎soc/arm/infineon_cat1/CMakeLists.txt‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(common/)
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add_subdirectory(${SOC_SERIES})

‎soc/arm/infineon_cat1/Kconfig‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_INFINEON_CAT1
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bool
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config SOC_FAMILY_INFINEON_CAT1A
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bool
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if SOC_FAMILY_INFINEON_CAT1
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source "soc/arm/infineon_cat1/*/Kconfig.soc"
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config SOC_FAMILY
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string
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default "infineon_cat1"
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endif # SOC_FAMILY_INFINEON_CAT1

‎soc/arm/infineon_cat1/Kconfig.defconfig‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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source "soc/arm/infineon_cat1/*/Kconfig.defconfig"

‎soc/arm/infineon_cat1/Kconfig.soc‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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source "soc/arm/infineon_cat1/*/Kconfig.series"

‎soc/arm/infineon_cat1/psoc6/CMakeLists.txt‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c)
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zephyr_include_directories(.)
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# Add sections
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zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT noinit.ld)
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# Add section for cm0p image ROM
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zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0 rom_cm0image.ld)
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# Add section for cm0p image RAM
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zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 ram_cm0image.ld)

‎soc/arm/infineon_cat1/psoc6/Kconfig.defconfig‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_INFINEON_CAT1
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source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*"
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config SOC_SERIES
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default "psoc6"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 100000000
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config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE
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hex
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default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
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config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE
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hex
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default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
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endif # SOC_FAMILY_INFINEON_CAT1A

‎soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*"

‎soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02‎

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# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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# Infineon PSoC6_02 based MCU default configuration
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if SOC_DIE_PSOC6_02
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config NUM_IRQS
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default 32 if CPU_CORTEX_M0PLUS
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default 168 if CPU_CORTEX_M4
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config SOC
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default "CYB0644ABZI_S2D44" if SOC_CYB0644ABZI_S2D44
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default "CYS0644ABZI_S2D44" if SOC_CYS0644ABZI_S2D44
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default "CY8C624ABZI_S2D44A0" if SOC_CY8C624ABZI_S2D44A0
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default "CY8C624ABZI_S2D44" if SOC_CY8C624ABZI_S2D44
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default "CY8C624AAZI_S2D44" if SOC_CY8C624AAZI_S2D44
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default "CY8C624AFNI_S2D43" if SOC_CY8C624AFNI_S2D43
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default "CY8C624ABZI_S2D04" if SOC_CY8C624ABZI_S2D04
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default "CY8C624ABZI_S2D14" if SOC_CY8C624ABZI_S2D14
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default "CY8C624AAZI_S2D14" if SOC_CY8C624AAZI_S2D14
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default "CY8C6248AZI_S2D14" if SOC_CY8C6248AZI_S2D14
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default "CY8C6248BZI_S2D44" if SOC_CY8C6248BZI_S2D44
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default "CY8C6248AZI_S2D44" if SOC_CY8C6248AZI_S2D44
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default "CY8C6248FNI_S2D43" if SOC_CY8C6248FNI_S2D43
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default "CY8C614ABZI_S2F04" if SOC_CY8C614ABZI_S2F04
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default "CY8C614AAZI_S2F04" if SOC_CY8C614AAZI_S2F04
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default "CY8C614AFNI_S2F03" if SOC_CY8C614AFNI_S2F03
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default "CY8C614AAZI_S2F14" if SOC_CY8C614AAZI_S2F14
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default "CY8C614ABZI_S2F44" if SOC_CY8C614ABZI_S2F44
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default "CY8C614AAZI_S2F44" if SOC_CY8C614AAZI_S2F44
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default "CY8C614AFNI_S2F43" if SOC_CY8C614AFNI_S2F43
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default "CY8C6148BZI_S2F44" if SOC_CY8C6148BZI_S2F44
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default "CY8C6148AZI_S2F44" if SOC_CY8C6148AZI_S2F44
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default "CY8C6148FNI_S2F43" if SOC_CY8C6148FNI_S2F43
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default "CY8C624ABZI_D44" if SOC_CY8C624ABZI_D44
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default "CY8C624ALQI_S2D42" if SOC_CY8C624ALQI_S2D42
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default "CY8C624ALQI_S2D02" if SOC_CY8C624ALQI_S2D02
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default "CY8C6248LQI_S2D42" if SOC_CY8C6248LQI_S2D42
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default "CY8C6248LQI_S2D02" if SOC_CY8C6248LQI_S2D02
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default "CY8C614ALQI_S2F42" if SOC_CY8C614ALQI_S2F42
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default "CY8C614ALQI_S2F02" if SOC_CY8C614ALQI_S2F02
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default "CY8C6148LQI_S2F42" if SOC_CY8C6148LQI_S2F42
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default "CY8C6148LQI_S2F02" if SOC_CY8C6148LQI_S2F02
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# add additional die specific params
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endif # SOC_DIE_PSOC6_02

‎soc/arm/infineon_cat1/psoc6/Kconfig.series‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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# Cypress PSoC™ 6 MCU lines
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config SOC_SERIES_PSOC_60
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bool "Infineon PSoC™ 60 series MCU(Value Line)"
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select SOC_FAMILY_INFINEON_CAT1
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help
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Enable support for Infineon PSoC™ 60 MCU series
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config SOC_SERIES_PSOC_61
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bool "Infineon PSoC™ 61 series MCU (Programmable Line)"
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select SOC_FAMILY_INFINEON_CAT1
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help
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Enable support for Infineon PSoC™ 61 MCU series
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config SOC_SERIES_PSOC_62
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bool "Infineon PSoC™ 62 series MCU (Performance Line)"
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select SOC_FAMILY_INFINEON_CAT1
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help
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Enable support for Infineon PSoC™ 62 MCU series
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config SOC_SERIES_PSOC_63
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bool "Infineon PSoC™ 63 series MCU (Connectivity Line)"
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select SOC_FAMILY_INFINEON_CAT1
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help
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Enable support for Infineon PSoC™ 63 MCU series
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config SOC_SERIES_PSOC_64
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bool "Infineon PSoC™ 64 series MCU (Security Line)"
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select SOC_FAMILY_INFINEON_CAT1
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help
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Enable support for Infineon PSoC™ 64 MCU series

‎soc/arm/infineon_cat1/psoc6/Kconfig.soc‎

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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# Infineon PSoC6 die
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config SOC_DIE_PSOC6
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bool
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_INFINEON_CAT1A
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select DYNAMIC_INTERRUPTS
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# Infineon PSoC6_01 die
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config SOC_DIE_PSOC6_01
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bool
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select SOC_DIE_PSOC6
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# Infineon PSoC6_02 die
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config SOC_DIE_PSOC6_02
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bool
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select SOC_DIE_PSOC6
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# Infineon PSoC6_03 die
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config SOC_DIE_PSOC6_03
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bool
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select SOC_DIE_PSOC6
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# Infineon PSoC6_04 die
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config SOC_DIE_PSOC6_04
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bool
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select SOC_DIE_PSOC6
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# Infineon soc packages
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config SOC_PACKAGE_PSOC6_01_124_BGA
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bool
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config SOC_PACKAGE_PSOC6_01_116_BGA_BLE
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bool
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config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
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bool
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config SOC_PACKAGE_PSOC6_01_80_WLCSP
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bool
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config SOC_PACKAGE_PSOC6_01_116_BGA_USB
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bool
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config SOC_PACKAGE_PSOC6_01_124_BGA_SIP
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bool
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config SOC_PACKAGE_PSOC6_01_43_SMT
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bool
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config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
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bool
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config SOC_PACKAGE_PSOC6_01_68_QFN_BLE
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bool
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config SOC_PACKAGE_PSOC6_02_124_BGA
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bool
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config SOC_PACKAGE_PSOC6_02_128_TQFP
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bool
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config SOC_PACKAGE_PSOC6_02_100_WLCSP
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bool
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config SOC_PACKAGE_PSOC6_02_68_QFN
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bool
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config SOC_PACKAGE_PSOC6_03_100_TQFP
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bool
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config SOC_PACKAGE_PSOC6_03_68_QFN
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bool
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config SOC_PACKAGE_PSOC6_03_49_WLCSP
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bool
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config SOC_PACKAGE_PSOC6_04_64_TQFP
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bool
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config SOC_PACKAGE_PSOC6_04_68_QFN
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bool
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config SOC_PACKAGE_PSOC6_04_80_TQFP
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bool
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## Infineon MCUs
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choice
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prompt "MPN"
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osource "soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_*"
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endchoice
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if SOC_FAMILY_INFINEON_CAT1A
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## PSoC™ 6 Cortex M0+ prebuilt images
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choice
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prompt "PSoC™ 6 Cortex M0+ prebuilt images"
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help
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Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6
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dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
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config SOC_PSOC6_CM0P_IMAGE_SLEEP
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bool "DeepSleep"
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help
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DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE
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dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
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application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
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linker script.
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endchoice
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endif # SOC_FAMILY_INFINEON_CAT1A

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