tests: boards: nrf: dmm: Add timing measurements

Add timing measurement to the test to allow DMM profiling. Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>

Author: nordic-krch

tests/boards/nrf/dmm/boards/nrf5340dk_nrf5340_cpuapp.overlay

@@ -1,3 +1,9 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 / {
 aliases {
 dut-cache = &spi1;
@@ -52,3 +58,7 @@
 pinctrl-1 = <&spi3_sleep_alt>;
 pinctrl-names = "default", "sleep";
 };
+
+cycle_timer: &timer1 {
+status = "okay";
+};

tests/boards/nrf/dmm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -1,3 +1,9 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 / {
 aliases {
 dut-cache = &spi120;
@@ -58,3 +64,7 @@
 pinctrl-names = "default", "sleep";
 memory-regions = <&dma_fast_region>;
 };
+
+cycle_timer: &timer120 {
+status = "okay";
+};

tests/boards/nrf/dmm/prj.conf

@@ -1 +1,5 @@
 CONFIG_ZTEST=y
+CONFIG_ASSERT=n
+CONFIG_SPIN_VALIDATE=n
+CONFIG_TEST_EXTRA_STACK_SIZE=512
+CONFIG_COUNTER=y

tests/boards/nrf/dmm/src/main.c

@@ -9,9 +9,12 @@
 #include <zephyr/cache.h>
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
+#include <zephyr/drivers/counter.h>
 
 #include <dmm.h>
 
+#define IS_ALIGNED64(x) IS_ALIGNED(x, sizeof(uint64_t))
+
 #define DUT_CACHE DT_ALIAS(dut_cache)
 #define DUT_NOCACHE DT_ALIAS(dut_nocache)
 
@@ -57,13 +60,49 @@ static const struct dmm_test_region dmm_test_regions[DMM_TEST_REGION_COUNT] = {
 .size = DMM_TEST_GET_REG_SIZE(DUT_NOCACHE)
 },
 };
+static const struct device *counter = DEVICE_DT_GET(DT_NODELABEL(cycle_timer));
+static uint32_t t_delta;
+
+static uint32_t ts_get(void)
+{
+uint32_t t;
+
+(void)counter_get_value(counter, &t);
+return t;
+}
+
+static uint32_t ts_from_get(uint32_t from)
+{
+return ts_get() - from;
+}
+
+static uint32_t cyc_to_us(uint32_t cyc)
+{
+return counter_ticks_to_us(counter, cyc);
+}
+
+static uint32_t cyc_to_rem_ns(uint32_t cyc)
+{
+uint32_t us = counter_ticks_to_us(counter, cyc);
+uint32_t ns;
+
+cyc = cyc - counter_us_to_ticks(counter, (uint64_t)us);
+ns = counter_ticks_to_us(counter, 1000 * cyc);
+
+return ns;
+}
 
 static void *test_setup(void)
 {
 static struct dmm_fixture fixture;
+uint32_t t;
 
+counter_start(counter);
+t = ts_get();
+t_delta = ts_get() - t;
 memcpy(fixture.regions, dmm_test_regions, sizeof(dmm_test_regions));
 fixture.fill_value = 0x1;
+
 return &fixture;
 }
 
@@ -79,13 +118,25 @@ static bool dmm_buffer_in_region_check(struct dmm_test_region *dtr, void *buf, s
 }
 
 static void dmm_check_output_buffer(struct dmm_test_region *dtr, uint32_t *fill_value,
- void *data, size_t size, bool was_prealloc, bool is_cached)
+ void *data, size_t size, bool was_prealloc,
+ bool is_cached, bool print_report)
 {
 void *buf;
 int retval;
+uint32_t t;
+bool aligned;
 
 memset(data, (*fill_value)++, size);
+t = ts_get();
 retval = dmm_buffer_out_prepare(dtr->mem_reg, data, size, &buf);
+t = ts_from_get(t);
+aligned = IS_ALIGNED64(data) && IS_ALIGNED64(buf) && IS_ALIGNED64(size);
+
+if (print_report) {
+TC_PRINT("%saligned buffer out prepare size:%d buf:%p took %d.%dus (%d cycles)\n",
+aligned ? "" : "not ", size, buf, cyc_to_us(t), cyc_to_rem_ns(t), t);
+}
+
 zassert_ok(retval);
 if (IS_ENABLED(CONFIG_DCACHE) && is_cached) {
 zassert_true(IS_ALIGNED(buf, CONFIG_DCACHE_LINE_SIZE));
@@ -104,21 +155,37 @@ static void dmm_check_output_buffer(struct dmm_test_region *dtr, uint32_t *fill_
 sys_cache_data_invd_range(buf, size);
 zassert_mem_equal(buf, data, size);
 
+t = ts_get();
 retval = dmm_buffer_out_release(dtr->mem_reg, buf);
+t = ts_from_get(t);
+if (print_report) {
+TC_PRINT("buffer out release buf:%p size:%d took %d.%dus (%d cycles)\n",
+buf, size, cyc_to_us(t), cyc_to_rem_ns(t), t);
+}
 zassert_ok(retval);
 }
 
 static void dmm_check_input_buffer(struct dmm_test_region *dtr, uint32_t *fill_value,
- void *data, size_t size, bool was_prealloc, bool is_cached)
+ void *data, size_t size, bool was_prealloc,
+ bool is_cached, bool print_report)
 {
 void *buf;
 int retval;
+uint32_t t;
 uint8_t intermediate_buf[128];
+bool aligned;
 
-zassert_true(size < sizeof(intermediate_buf));
+zassert_true(size <= sizeof(intermediate_buf));
 
+t = ts_get();
 retval = dmm_buffer_in_prepare(dtr->mem_reg, data, size, &buf);
+t = ts_from_get(t);
+aligned = IS_ALIGNED64(data) && IS_ALIGNED64(buf) && IS_ALIGNED64(size);
 zassert_ok(retval);
+if (print_report) {
+TC_PRINT("%saligned buffer in prepare buf:%p size:%d took %d.%dus (%d cycles)\n",
+aligned ? "" : "not ", buf, size, cyc_to_us(t), cyc_to_rem_ns(t), t);
+}
 if (IS_ENABLED(CONFIG_DCACHE) && is_cached) {
 zassert_true(IS_ALIGNED(buf, CONFIG_DCACHE_LINE_SIZE));
 }
@@ -144,74 +211,130 @@ static void dmm_check_input_buffer(struct dmm_test_region *dtr, uint32_t *fill_v
 memset(buf, (*fill_value)++, size);
 }
 
+t = ts_get();
 retval = dmm_buffer_in_release(dtr->mem_reg, data, size, buf);
+t = ts_from_get(t);
+if (print_report) {
+TC_PRINT("buffer in release buf:%p size:%d took %d.%dus (%d cycles)\n",
+buf, size, cyc_to_us(t), cyc_to_rem_ns(t), t);
+}
 zassert_ok(retval);
 
 zassert_mem_equal(data, intermediate_buf, size);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_cache_in_allocate)
 {
-uint8_t user_data[16];
+uint8_t user_data[128] __aligned(sizeof(uint64_t));
 
 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
- user_data, sizeof(user_data), false, true);
+ user_data, 16, false, true, false);
+dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
+ user_data, 16, false, true, true);
+dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
+ user_data, sizeof(user_data), false, true, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_cache_in_preallocate)
 {
 static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_CACHE);
 
 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
- user_data, sizeof(user_data), true, true);
+ user_data, sizeof(user_data), true, true, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_cache_out_allocate)
 {
-uint8_t user_data[16];
+uint8_t user_data[129] __aligned(sizeof(uint64_t));
+
+/* First run to get code into ICACHE so that following runs has consistent timing. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
+user_data, 16, false, true, false);
 
+/* Aligned user buffer. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
+user_data, 16, false, true, true);
+/* Unaligned user buffer. */
 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
-user_data, sizeof(user_data), false, true);
+&user_data[1], 16, false, true, true);
+
+/* Aligned user buffer. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
+user_data, sizeof(user_data) - 1, false, true, true);
+/* Unaligned user buffer. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
+&user_data[1], sizeof(user_data) - 1, false, true, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_cache_out_preallocate)
 {
 static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_CACHE);
 
 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_CACHE], &fixture->fill_value,
-user_data, sizeof(user_data), true, true);
+user_data, sizeof(user_data), true, true, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_nocache_in_allocate)
 {
-uint8_t user_data[16];
+uint8_t user_data[129] __aligned(sizeof(uint64_t));
+
+dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+ user_data, 16, false, false, false);
+
+/* Aligned user buffer. */
+dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+ user_data, 16, false, false, true);
+
+/* Unaligned user buffer. */
+dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+ &user_data[1], 16, false, false, true);
 
+/* Aligned user buffer. */
 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
- user_data, sizeof(user_data), false, false);
+ user_data, sizeof(user_data) - 1, false, false, true);
+
+/* Unaligned user buffer. */
+dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+ &user_data[1], sizeof(user_data) - 1, false, false, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_nocache_in_preallocate)
 {
 static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_NOCACHE);
 
 dmm_check_input_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
- user_data, sizeof(user_data), true, false);
+ user_data, sizeof(user_data), true, false, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_nocache_out_allocate)
 {
-uint8_t user_data[16];
+uint8_t user_data[129] __aligned(sizeof(uint64_t));
 
+/* First run to get code into ICACHE so that following results are consistent. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+user_data, 16, false, false, false);
+
+/* Aligned user buffer. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+user_data, 16, false, false, true);
+/* Unaligned user buffer. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+&user_data[1], 16, false, false, true);
+
+/* Aligned user buffer. */
+dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
+user_data, sizeof(user_data) - 1, false, false, true);
+/* Unaligned user buffer. */
 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
-user_data, sizeof(user_data), false, false);
+&user_data[1], sizeof(user_data) - 1, false, false, true);
 }
 
 ZTEST_USER_F(dmm, test_check_dev_nocache_out_preallocate)
 {
 static uint8_t user_data[16] DMM_MEMORY_SECTION(DUT_NOCACHE);
 
 dmm_check_output_buffer(&fixture->regions[DMM_TEST_REGION_NOCACHE], &fixture->fill_value,
-user_data, sizeof(user_data), true, false);
+user_data, sizeof(user_data), true, false, true);
 }
 
 ZTEST_SUITE(dmm, NULL, test_setup, NULL, test_cleanup, NULL);