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Commits on Sep 18, 2021
rv32: Fix an issue which was causing linux to lockup on 32-bit timer overflow.
ultraembedded
committed
8a0528c
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Commits on Sep 16, 2021
- Add support for unaligned loads and stores.
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b014c61
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Commits on Jul 11, 2021
Add support for loading an initrd binary.
ultraembedded
committed
7f2c725
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Commits on Jun 5, 2021
Add 2nd executable that can load and run a S-MODE RISCV linux kernel image without any additional bootloaders. This includes very basic SBI support (0.1).
ultraembedded
committed
efad2e1
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Commits on Jun 1, 2021
Disable tap device (networking) unless built with HAS_NETWORK=True
ultraembedded
committed
78e71ba
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Commits on May 23, 2021
Update README.md
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authored
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Update README.md
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a1b4519
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Update build.yml
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7d4494d
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Create build.yml
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authored
e1008bf
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Update README to detail VirtIO support
ultraembedded
committed
e8ea42c
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Add support for virtio devices such as block device (disk in a file) and networking (using a TAP device).
ultraembedded
committed
9e7e475
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Commits on May 22, 2021
Switch fgetc() to read().
ultraembedded
committed
869bb7e
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Commits on Nov 8, 2020
MIPS: Fix unaligned load / store instruction support. Add some more debug hooks used for cosimulation purposes.
ultraembedded
committed
3ec28af
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Commits on Oct 29, 2020
Add basic MIPS (MIPS-i ISA) support. Runs some code, but very limited testing of interrupts, exceptions. Expect bugs.
ultraembedded
committed
0ad9b8b
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Commits on Jun 21, 2020
Add simple-framebuffer device support (using SDL). Only supports RGB565 for now. Enabled if HAS_SCREEN=True is set whilst building.
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a28cea8
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Commits on Mar 14, 2020
Add support for CSR_SIM_CTRL register which can be accessed by any priv level. Add support for dumping registers to file after executing. Make entry into some faults more predictable (improved cosi…
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6d9d6a3
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Commits on Mar 3, 2020
Add option for non-std built in mtimer interrupt (for emulating systems which do not have the CLINT timer). Enable invalid instruction emulation.
ultraembedded
committed
1e790d4
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Commits on Feb 25, 2020
Bug fix for supervisor mode being able to overwrite machine mode CSRs (mie, mip, mstatus)
ultraembedded
committed
3b436ca
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Commits on Feb 23, 2020
Add CPU_INTERRUPT_MEIP_ONLY compile flag for forcing more predictable interrupts for cosimulation.
ultraembedded
committed
7f4844f
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Add option to modify interrupt behaviour for cosimulation purposes.
ultraembedded
committed
1fc7a3d
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Commits on Feb 17, 2020
Make instruction fetches identifiable from load / stores for cosimulation purposes
ultraembedded
committed
50cabd1
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Use write16, read16 as appropriate instead of multiple read/write8
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committed
2902883
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Commits on Dec 15, 2019
Support for exiting on hitting a given symbol name PC
ultraembedded
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e0d8803
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Logging: Differentiate conditional branches from unconditional jumps
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5cad1db
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Commits on Dec 8, 2019
Cleanup README
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19ec215
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Add logging callback functions for branches and exceptions.
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0d5e0a1
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Commits on Nov 26, 2019
Add virtual function for monitoring completed instructions
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3500282
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Commits on Nov 25, 2019
Add TLBs to increase performance of simulator
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1011429
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Commits on Nov 24, 2019
Fix bug relating to duplicate memories being allocated in some cases.
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c16f9e4
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Commits on Nov 12, 2019
Add details to README relating to running Linux
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2b10549
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Commits on Nov 10, 2019
RV64: Fixes to interrupt handling (incorrect mcause implementation)
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14be45c
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RV64: Add MMU support (based on RV32 implementation with number of levels changed).
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05c37de
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Commits on Nov 9, 2019
Minor README tweak
ultraembedded
committed
657388f
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Allow CSR behaviour to be change (virtual function).
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committed
5d7e6fa
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Simplify device tree handling
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92443cd
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