Implement Tx only Flush (espressif#3433)

* add option to Flush() to only clear txQueue Add the option to cause Flush() to just wait for tx data to clear the tx fifo and uart, leave the rx queue and rx fifo as is. * support tx only flush() * support tx only Flush() * support txOnly for Flush() * compatibility to Stream() * compatibility for Stream() * default value error * default value error * Update esp32-hal-uart.h * Update esp32-hal-uart.c * Update HardwareSerial.cpp * sp * correctly implement flushTxOnly()

Author: stickbreaker

cores/esp32/HardwareSerial.cpp

@@ -131,11 +131,16 @@ int HardwareSerial::read(void)
  return -1;
 }
 
-void HardwareSerial::flush()
+void HardwareSerial::flush(void)
 {
  uartFlush(_uart);
 }
 
+void HardwareSerial::flush(bool txOnly)
+{
+ uartFlushTxOnly(_uart, txOnly);
+}
+
 size_t HardwareSerial::write(uint8_t c)
 {
  uartWrite(_uart, c);

cores/esp32/HardwareSerial.h

@@ -63,6 +63,7 @@ class HardwareSerial: public Stream
  int peek(void);
  int read(void);
  void flush(void);
+ void flush( bool txOnly);
  size_t write(uint8_t);
  size_t write(const uint8_t *buffer, size_t size);
 

cores/esp32/esp32-hal-uart.c

@@ -327,24 +327,31 @@ void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len)
 }
 
 void uartFlush(uart_t* uart)
+{
+ uartFlushTxOnly(uart,false);
+}
+
+void uartFlushTxOnly(uart_t* uart, bool txOnly)
 {
  if(uart == NULL) {
  return;
  }
 
  UART_MUTEX_LOCK();
  while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
+ 
+ if( !txOnly ){
+ //Due to hardware issue, we can not use fifo_rst to reset uart fifo.
+ //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
 
- //Due to hardware issue, we can not use fifo_rst to reset uart fifo.
- //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
+ // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
+ while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
+ READ_PERI_REG(UART_FIFO_REG(uart->num));
+ }
 
- // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
- while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
- READ_PERI_REG(UART_FIFO_REG(uart->num));
+ xQueueReset(uart->queue);
  }
-
- xQueueReset(uart->queue);
-
+ 
  UART_MUTEX_UNLOCK();
 }
 

cores/esp32/esp32-hal-uart.h

@@ -63,6 +63,7 @@ void uartWrite(uart_t* uart, uint8_t c);
 void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len);
 
 void uartFlush(uart_t* uart);
+void uartFlushTxOnly(uart_t* uart, bool txOnly );
 
 void uartSetBaudRate(uart_t* uart, uint32_t baud_rate);
 uint32_t uartGetBaudRate(uart_t* uart);