HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

RTL data structure

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

16 bit serial multiplier in SystemVerilog

Synthesizable SystemVerilog IP-Core of the I2S Receiver

Pulse Width Modulator programmed through an Advanced Peripheral Bus interface

UVM Test bench for a 8-bit ALU

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board

RISC-V five stage pipline CPU

A systemverilog implementation of the data structures: priority queue, queue and stack

This testbench is based on SV and UVM Class based to verify Verilog HDL Design

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.

An FPGA-based Chess Engine and TPU

Multiple DUT with parallel stimulus

A project to implement and test simple SRAM synchronous positive edge memory.