1- /* Print last reset reason of ESP32
2- * by Evandro Luis Copercini - 2017
1+ /*
2+ * Print last reset reason of ESP32
3+ * =================================
4+ *
5+ * Use either of the methods print_reset_reason
6+ * or verbose_print_reset_reason to display the
7+ * cause for the last reset of this device.
8+ *
39* Public Domain License.
10+ *
11+ * Author:
12+ * Evandro Luis Copercini - 2017
413*/
514
615#include < rom/rtc.h>
716
17+ #define uS_TO_S_FACTOR 1000000 /* Conversion factor for micro seconds to seconds */
18+
819void print_reset_reason (RESET_REASON reason)
920{
1021 switch ( reason)
@@ -28,20 +39,109 @@ void print_reset_reason(RESET_REASON reason)
2839 }
2940}
3041
42+ void verbose_print_reset_reason (RESET_REASON reason)
43+ {
44+ switch ( reason)
45+ {
46+ case 1 : Serial.println (" Vbat power on reset" );break ;
47+ case 3 : Serial.println (" Software reset digital core" );break ;
48+ case 4 : Serial.println (" Legacy watch dog reset digital core" );break ;
49+ case 5 : Serial.println (" Deep Sleep reset digital core" );break ;
50+ case 6 : Serial.println (" Reset by SLC module, reset digital core" );break ;
51+ case 7 : Serial.println (" Timer Group0 Watch dog reset digital core" );break ;
52+ case 8 : Serial.println (" Timer Group1 Watch dog reset digital core" );break ;
53+ case 9 : Serial.println (" RTC Watch dog Reset digital core" );break ;
54+ case 10 : Serial.println (" Instrusion tested to reset CPU" );break ;
55+ case 11 : Serial.println (" Time Group reset CPU" );break ;
56+ case 12 : Serial.println (" Software reset CPU" );break ;
57+ case 13 : Serial.println (" RTC Watch dog Reset CPU" );break ;
58+ case 14 : Serial.println (" for APP CPU, reseted by PRO CPU" );break ;
59+ case 15 : Serial.println (" Reset when the vdd voltage is not stable" );break ;
60+ case 16 : Serial.println (" RTC Watch dog reset digital core and rtc module" );break ;
61+ default : Serial.println (" NO_MEAN" );
62+ }
63+ }
64+
3165void setup () {
3266 // put your setup code here, to run once:
3367 Serial.begin (115200 );
3468 delay (2000 );
3569
36- Serial.println (" CPU0 reset reason: " );
70+ Serial.println (" CPU0 reset reason:" );
3771 print_reset_reason (rtc_get_reset_reason (0 ));
72+ verbose_print_reset_reason (rtc_get_reset_reason (0 ));
3873
39- Serial.println (" CPU1 reset reason: " );
74+ Serial.println (" CPU1 reset reason:" );
4075 print_reset_reason (rtc_get_reset_reason (1 ));
76+ verbose_print_reset_reason (rtc_get_reset_reason (1 ));
4177
78+ // Set ESP32 to go to deep sleep to see a variation
79+ // in the reset reason. Device will sleep for 5 seconds.
80+ esp_deep_sleep_pd_config (ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
81+ Serial.println (" Going to sleep" );
82+ esp_deep_sleep (5 * uS_TO_S_FACTOR);
4283}
4384
4485void loop () {
4586 // put your main code here, to run repeatedly:
4687
47- }
88+ }
89+
90+ /*
91+ Example Serial Log:
92+ ====================
93+
94+ rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
95+ configsip: 0, SPIWP:0x00
96+ clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
97+ mode:DIO, clock div:1
98+ load:0x3fff0008,len:8
99+ load:0x3fff0010,len:160
100+ load:0x40078000,len:10632
101+ load:0x40080000,len:252
102+ entry 0x40080034
103+ CPU0 reset reason:
104+ RTCWDT_RTC_RESET
105+ RTC Watch dog reset digital core and rtc module
106+ CPU1 reset reason:
107+ EXT_CPU_RESET
108+ for APP CPU, reseted by PRO CPU
109+ Going to sleep
110+ ets Jun 8 2016 00:22:57
111+
112+ rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
113+ configsip: 0, SPIWP:0x00
114+ clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
115+ mode:DIO, clock div:1
116+ load:0x3fff0008,len:8
117+ load:0x3fff0010,len:160
118+ load:0x40078000,len:10632
119+ load:0x40080000,len:252
120+ entry 0x40080034
121+ CPU0 reset reason:
122+ DEEPSLEEP_RESET
123+ Deep Sleep reset digital core
124+ CPU1 reset reason:
125+ EXT_CPU_RESET
126+ for APP CPU, reseted by PRO CPU
127+ Going to sleep
128+ ets Jun 8 2016 00:22:57
129+
130+ rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
131+ configsip: 0, SPIWP:0x00
132+ clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
133+ mode:DIO, clock div:1
134+ load:0x3fff0008,len:8
135+ load:0x3fff0010,len:160
136+ load:0x40078000,len:10632
137+ load:0x40080000,len:252
138+ entry 0x40080034
139+ CPU0 reset reason:
140+ DEEPSLEEP_RESET
141+ Deep Sleep reset digital core
142+ CPU1 reset reason:
143+ EXT_CPU_RESET
144+ for APP CPU, reseted by PRO CPU
145+ Going to sleep
146+
147+ */
0 commit comments