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jit: Enhance security by Control-Flow Integrity

researchStudy certain topicsStudy certain topics

Status: Open.

#311 In sysprog21/rv32emu;

· jserv opened on Dec 28, 2023

Evaluate a hybrid approach for macro-operation fusion in both the decoding and execution stages

enhancementNew feature or requestNew feature or request

Status: Open.

#298 In sysprog21/rv32emu;

· jserv opened on Dec 17, 2023

Compare with libriscv

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Status: Open.

#288 In sysprog21/rv32emu;

· jserv opened on Dec 9, 2023

Evaluate effectiveness of dynamic superinstructions

researchStudy certain topicsStudy certain topics

Status: Open.

#282 In sysprog21/rv32emu;

· jserv opened on Nov 29, 2023

Evaluate block replacement algorithms which receive attention on improvement of hit ratio

researchStudy certain topicsStudy certain topics

Status: Open.

#200 In sysprog21/rv32emu;

· jserv opened on Aug 30, 2023

Generate RISC-V instruction decoder from ISA descriptor

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#103 In sysprog21/rv32emu;

· jserv opened on Jan 2, 2023

Integrate deterministic memory pool

enhancementNew feature or requestNew feature or request

Status: Open.

#94 In sysprog21/rv32emu;

· jserv opened on Dec 12, 2022

Use portable JIT compilation for accelerating RISC-V emulation

researchStudy certain topicsStudy certain topics

Status: Open.

#81 In sysprog21/rv32emu;

· jserv opened on Nov 4, 2022

Integrate <code>embench-iot</code> for benchmarking

Status: Open.

#28 In sysprog21/rv32emu;

· jserv opened on Aug 2, 2022