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[RISCV] Prioritize Qualcomm uC Xqcics over Xqcicli (llvm#162416)
In cases where both Xqcics and Xqcicli patterns can be used, Xqcics should be used because some instructions in this extension are commutable.
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-50
lines changed

5 files changed

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lines changed

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1520,6 +1520,8 @@ def HasVendorXqcics
15201520
: Predicate<"Subtarget->hasVendorXqcics()">,
15211521
AssemblerPredicate<(all_of FeatureVendorXqcics),
15221522
"'Xqcics' (Qualcomm uC Conditional Select Extension)">;
1523+
def NoVendorXqcics
1524+
: Predicate<"!Subtarget->hasVendorXqcics()">;
15231525

15241526
def FeatureVendorXqcicsr
15251527
: RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1571,35 +1571,42 @@ def : QCIMVCCIPat<SETUGE, QC_MVGEUI, uimm5nonzero>;
15711571
}
15721572

15731573
let Predicates = [HasVendorXqcicli, IsRV32] in {
1574-
def : QCILICCPat<SETEQ, QC_LIEQ>;
1575-
def : QCILICCPat<SETNE, QC_LINE>;
15761574
def : QCILICCPat<SETLT, QC_LILT>;
15771575
def : QCILICCPat<SETGE, QC_LIGE>;
15781576
def : QCILICCPat<SETULT, QC_LILTU>;
15791577
def : QCILICCPat<SETUGE, QC_LIGEU>;
15801578

1581-
def : QCILICCIPat<SETEQ, QC_LIEQI, simm5>;
1582-
def : QCILICCIPat<SETNE, QC_LINEI, simm5>;
15831579
def : QCILICCIPat<SETLT, QC_LILTI, simm5>;
15841580
def : QCILICCIPat<SETGE, QC_LIGEI, simm5>;
15851581
def : QCILICCIPat<SETULT, QC_LILTUI, uimm5>;
15861582
def : QCILICCIPat<SETUGE, QC_LIGEUI, uimm5>;
15871583

1588-
def : QCILICCPatInv<SETNE, QC_LIEQ>;
1589-
def : QCILICCPatInv<SETEQ, QC_LINE>;
15901584
def : QCILICCPatInv<SETGE, QC_LILT>;
15911585
def : QCILICCPatInv<SETLT, QC_LIGE>;
15921586
def : QCILICCPatInv<SETUGE, QC_LILTU>;
15931587
def : QCILICCPatInv<SETULT, QC_LIGEU>;
15941588

1595-
def : QCILICCIPatInv<SETNE, QC_LIEQI, simm5>;
1596-
def : QCILICCIPatInv<SETEQ, QC_LINEI, simm5>;
15971589
def : QCILICCIPatInv<SETGE, QC_LILTI, simm5>;
15981590
def : QCILICCIPatInv<SETLT, QC_LIGEI, simm5>;
15991591
def : QCILICCIPatInv<SETUGE, QC_LILTUI, uimm5>;
16001592
def : QCILICCIPatInv<SETULT, QC_LIGEUI, uimm5>;
16011593
} // Predicates = [HasVendorXqcicli, IsRV32]
16021594

1595+
// Prioritize Xqcics over these patterns.
1596+
let Predicates = [HasVendorXqcicli, NoVendorXqcics, IsRV32] in {
1597+
def : QCILICCPat<SETEQ, QC_LIEQ>;
1598+
def : QCILICCPat<SETNE, QC_LINE>;
1599+
1600+
def : QCILICCIPat<SETEQ, QC_LIEQI, simm5>;
1601+
def : QCILICCIPat<SETNE, QC_LINEI, simm5>;
1602+
1603+
def : QCILICCPatInv<SETNE, QC_LIEQ>;
1604+
def : QCILICCPatInv<SETEQ, QC_LINE>;
1605+
1606+
def : QCILICCIPatInv<SETNE, QC_LIEQI, simm5>;
1607+
def : QCILICCIPatInv<SETEQ, QC_LINEI, simm5>;
1608+
} // Predicates = [HasVendorXqcicli, NoVendorXqcics, IsRV32]
1609+
16031610
let Predicates = [HasVendorXqcics, IsRV32] in {
16041611
// (SELECT X, Y, Z) is canonicalised to `(riscv_selectcc x, 0, NE, y, z)`.
16051612
// These exist to prioritise over the `Select_GPR_Using_CC_GPR` pattern.

‎llvm/test/CodeGen/RISCV/cmov-branch-opt.ll‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -201,8 +201,9 @@ define signext i32 @test4(i32 signext %x, i32 signext %y, i32 signext %z) {
201201
;
202202
; RV32IXQCI-LABEL: test4:
203203
; RV32IXQCI: # %bb.0:
204-
; RV32IXQCI-NEXT: li a0, 0
205-
; RV32IXQCI-NEXT: qc.lieqi a0, a2, 0, 3
204+
; RV32IXQCI-NEXT: mv a0, a2
205+
; RV32IXQCI-NEXT: li a1, 3
206+
; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 0
206207
; RV32IXQCI-NEXT: ret
207208
%c = icmp eq i32 %z, 0
208209
%a = select i1 %c, i32 3, i32 0

‎llvm/test/CodeGen/RISCV/xqcicli.ll‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,8 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
2323
;
2424
; RV32IXQCI-LABEL: select_cc_example_eq:
2525
; RV32IXQCI: # %bb.0: # %entry
26-
; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11
26+
; RV32IXQCI-NEXT: qc.selectine a1, a2, a0, 11
27+
; RV32IXQCI-NEXT: mv a0, a1
2728
; RV32IXQCI-NEXT: ret
2829
entry:
2930
%cmp = icmp eq i32 %b, %x
@@ -47,7 +48,8 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
4748
;
4849
; RV32IXQCI-LABEL: select_cc_example_ne:
4950
; RV32IXQCI: # %bb.0: # %entry
50-
; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11
51+
; RV32IXQCI-NEXT: qc.selectieq a1, a2, a0, 11
52+
; RV32IXQCI-NEXT: mv a0, a1
5153
; RV32IXQCI-NEXT: ret
5254
entry:
5355
%cmp = icmp ne i32 %b, %x
@@ -167,7 +169,8 @@ define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
167169
;
168170
; RV32IXQCI-LABEL: select_cc_example_eq_c:
169171
; RV32IXQCI: # %bb.0: # %entry
170-
; RV32IXQCI-NEXT: qc.line a0, a1, a2, 11
172+
; RV32IXQCI-NEXT: qc.selectieq a1, a2, a0, 11
173+
; RV32IXQCI-NEXT: mv a0, a1
171174
; RV32IXQCI-NEXT: ret
172175
entry:
173176
%cmp = icmp eq i32 %b, %x
@@ -191,7 +194,8 @@ define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
191194
;
192195
; RV32IXQCI-LABEL: select_cc_example_ne_c:
193196
; RV32IXQCI: # %bb.0: # %entry
194-
; RV32IXQCI-NEXT: qc.lieq a0, a1, a2, 11
197+
; RV32IXQCI-NEXT: qc.selectine a1, a2, a0, 11
198+
; RV32IXQCI-NEXT: mv a0, a1
195199
; RV32IXQCI-NEXT: ret
196200
entry:
197201
%cmp = icmp ne i32 %b, %x
@@ -312,7 +316,8 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
312316
;
313317
; RV32IXQCI-LABEL: select_cc_example_eqi:
314318
; RV32IXQCI: # %bb.0: # %entry
315-
; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
319+
; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11
320+
; RV32IXQCI-NEXT: mv a0, a1
316321
; RV32IXQCI-NEXT: ret
317322
entry:
318323
%cmp = icmp eq i32 %b, 12
@@ -337,7 +342,8 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
337342
;
338343
; RV32IXQCI-LABEL: select_cc_example_nei:
339344
; RV32IXQCI: # %bb.0: # %entry
340-
; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
345+
; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11
346+
; RV32IXQCI-NEXT: mv a0, a1
341347
; RV32IXQCI-NEXT: ret
342348
entry:
343349
%cmp = icmp ne i32 %b, 12
@@ -462,7 +468,8 @@ define i32 @select_cc_example_eqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
462468
;
463469
; RV32IXQCI-LABEL: select_cc_example_eqi_c1:
464470
; RV32IXQCI: # %bb.0: # %entry
465-
; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
471+
; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11
472+
; RV32IXQCI-NEXT: mv a0, a1
466473
; RV32IXQCI-NEXT: ret
467474
entry:
468475
%cmp = icmp eq i32 12, %b
@@ -487,7 +494,8 @@ define i32 @select_cc_example_nei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
487494
;
488495
; RV32IXQCI-LABEL: select_cc_example_nei_c1:
489496
; RV32IXQCI: # %bb.0: # %entry
490-
; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
497+
; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11
498+
; RV32IXQCI-NEXT: mv a0, a1
491499
; RV32IXQCI-NEXT: ret
492500
entry:
493501
%cmp = icmp ne i32 12, %b
@@ -612,7 +620,8 @@ define i32 @select_cc_example_eqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
612620
;
613621
; RV32IXQCI-LABEL: select_cc_example_eqi_c2:
614622
; RV32IXQCI: # %bb.0: # %entry
615-
; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
623+
; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11
624+
; RV32IXQCI-NEXT: mv a0, a1
616625
; RV32IXQCI-NEXT: ret
617626
entry:
618627
%cmp = icmp eq i32 12, %b
@@ -637,7 +646,8 @@ define i32 @select_cc_example_nei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
637646
;
638647
; RV32IXQCI-LABEL: select_cc_example_nei_c2:
639648
; RV32IXQCI: # %bb.0: # %entry
640-
; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
649+
; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11
650+
; RV32IXQCI-NEXT: mv a0, a1
641651
; RV32IXQCI-NEXT: ret
642652
entry:
643653
%cmp = icmp ne i32 12, %b
@@ -762,7 +772,8 @@ define i32 @select_cc_example_eqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
762772
;
763773
; RV32IXQCI-LABEL: select_cc_example_eqi_c3:
764774
; RV32IXQCI: # %bb.0: # %entry
765-
; RV32IXQCI-NEXT: qc.linei a0, a1, 12, 11
775+
; RV32IXQCI-NEXT: qc.selectieqi a1, 12, a0, 11
776+
; RV32IXQCI-NEXT: mv a0, a1
766777
; RV32IXQCI-NEXT: ret
767778
entry:
768779
%cmp = icmp eq i32 %b, 12
@@ -787,7 +798,8 @@ define i32 @select_cc_example_nei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
787798
;
788799
; RV32IXQCI-LABEL: select_cc_example_nei_c3:
789800
; RV32IXQCI: # %bb.0: # %entry
790-
; RV32IXQCI-NEXT: qc.lieqi a0, a1, 12, 11
801+
; RV32IXQCI-NEXT: qc.selectinei a1, 12, a0, 11
802+
; RV32IXQCI-NEXT: mv a0, a1
791803
; RV32IXQCI-NEXT: ret
792804
entry:
793805
%cmp = icmp ne i32 %b, 12

‎llvm/test/CodeGen/RISCV/xqcics.ll‎

Lines changed: 14 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -270,8 +270,7 @@ define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
270270
;
271271
; RV32IXQCI-LABEL: select_cc_example_eqi:
272272
; RV32IXQCI: # %bb.0: # %entry
273-
; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
274-
; RV32IXQCI-NEXT: mv a0, a2
273+
; RV32IXQCI-NEXT: qc.selectieq a0, a1, a2, 11
275274
; RV32IXQCI-NEXT: ret
276275
entry:
277276
%cmp = icmp eq i32 %a, %b
@@ -301,8 +300,7 @@ define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
301300
;
302301
; RV32IXQCI-LABEL: select_cc_example_eqi_c:
303302
; RV32IXQCI: # %bb.0: # %entry
304-
; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
305-
; RV32IXQCI-NEXT: mv a0, a2
303+
; RV32IXQCI-NEXT: qc.selectine a0, a1, a2, 11
306304
; RV32IXQCI-NEXT: ret
307305
entry:
308306
%cmp = icmp eq i32 %a, %b
@@ -332,8 +330,7 @@ define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
332330
;
333331
; RV32IXQCI-LABEL: select_cc_example_nei:
334332
; RV32IXQCI: # %bb.0: # %entry
335-
; RV32IXQCI-NEXT: qc.lieq a2, a0, a1, 11
336-
; RV32IXQCI-NEXT: mv a0, a2
333+
; RV32IXQCI-NEXT: qc.selectine a0, a1, a2, 11
337334
; RV32IXQCI-NEXT: ret
338335
entry:
339336
%cmp = icmp ne i32 %a, %b
@@ -363,8 +360,7 @@ define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
363360
;
364361
; RV32IXQCI-LABEL: select_cc_example_nei_c:
365362
; RV32IXQCI: # %bb.0: # %entry
366-
; RV32IXQCI-NEXT: qc.line a2, a0, a1, 11
367-
; RV32IXQCI-NEXT: mv a0, a2
363+
; RV32IXQCI-NEXT: qc.selectieq a0, a1, a2, 11
368364
; RV32IXQCI-NEXT: ret
369365
entry:
370366
%cmp = icmp ne i32 %a, %b
@@ -395,8 +391,7 @@ define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
395391
;
396392
; RV32IXQCI-LABEL: select_cc_example_ieqi:
397393
; RV32IXQCI: # %bb.0: # %entry
398-
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
399-
; RV32IXQCI-NEXT: mv a0, a2
394+
; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11
400395
; RV32IXQCI-NEXT: ret
401396
entry:
402397
%cmp = icmp eq i32 %a, 12
@@ -427,8 +422,7 @@ define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
427422
;
428423
; RV32IXQCI-LABEL: select_cc_example_ieqi_c1:
429424
; RV32IXQCI: # %bb.0: # %entry
430-
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
431-
; RV32IXQCI-NEXT: mv a0, a2
425+
; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11
432426
; RV32IXQCI-NEXT: ret
433427
entry:
434428
%cmp = icmp eq i32 12, %a
@@ -459,8 +453,7 @@ define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
459453
;
460454
; RV32IXQCI-LABEL: select_cc_example_ieqi_c2:
461455
; RV32IXQCI: # %bb.0: # %entry
462-
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
463-
; RV32IXQCI-NEXT: mv a0, a2
456+
; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11
464457
; RV32IXQCI-NEXT: ret
465458
entry:
466459
%cmp = icmp eq i32 %a, 12
@@ -491,8 +484,7 @@ define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
491484
;
492485
; RV32IXQCI-LABEL: select_cc_example_ieqi_c3:
493486
; RV32IXQCI: # %bb.0: # %entry
494-
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
495-
; RV32IXQCI-NEXT: mv a0, a2
487+
; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11
496488
; RV32IXQCI-NEXT: ret
497489
entry:
498490
%cmp = icmp eq i32 12, %a
@@ -523,8 +515,7 @@ define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
523515
;
524516
; RV32IXQCI-LABEL: select_cc_example_inei:
525517
; RV32IXQCI: # %bb.0: # %entry
526-
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
527-
; RV32IXQCI-NEXT: mv a0, a2
518+
; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11
528519
; RV32IXQCI-NEXT: ret
529520
entry:
530521
%cmp = icmp ne i32 %a, 12
@@ -555,8 +546,7 @@ define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
555546
;
556547
; RV32IXQCI-LABEL: select_cc_example_inei_c1:
557548
; RV32IXQCI: # %bb.0: # %entry
558-
; RV32IXQCI-NEXT: qc.lieqi a2, a0, 12, 11
559-
; RV32IXQCI-NEXT: mv a0, a2
549+
; RV32IXQCI-NEXT: qc.selectinei a0, 12, a2, 11
560550
; RV32IXQCI-NEXT: ret
561551
entry:
562552
%cmp = icmp ne i32 12, %a
@@ -587,8 +577,7 @@ define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
587577
;
588578
; RV32IXQCI-LABEL: select_cc_example_inei_c2:
589579
; RV32IXQCI: # %bb.0: # %entry
590-
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
591-
; RV32IXQCI-NEXT: mv a0, a2
580+
; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11
592581
; RV32IXQCI-NEXT: ret
593582
entry:
594583
%cmp = icmp ne i32 %a, 12
@@ -619,8 +608,7 @@ define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
619608
;
620609
; RV32IXQCI-LABEL: select_cc_example_inei_c3:
621610
; RV32IXQCI: # %bb.0: # %entry
622-
; RV32IXQCI-NEXT: qc.linei a2, a0, 12, 11
623-
; RV32IXQCI-NEXT: mv a0, a2
611+
; RV32IXQCI-NEXT: qc.selectieqi a0, 12, a2, 11
624612
; RV32IXQCI-NEXT: ret
625613
entry:
626614
%cmp = icmp ne i32 12, %a
@@ -712,8 +700,7 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
712700
;
713701
; RV32IXQCI-LABEL: select_cc_example_eq1:
714702
; RV32IXQCI: # %bb.0: # %entry
715-
; RV32IXQCI-NEXT: qc.line a2, a1, a0, 11
716-
; RV32IXQCI-NEXT: mv a0, a2
703+
; RV32IXQCI-NEXT: qc.selectieq a0, a1, a2, 11
717704
; RV32IXQCI-NEXT: ret
718705
entry:
719706
%cmp = icmp eq i32 %b, %a
@@ -743,8 +730,7 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
743730
;
744731
; RV32IXQCI-LABEL: select_cc_example_ne1:
745732
; RV32IXQCI: # %bb.0: # %entry
746-
; RV32IXQCI-NEXT: qc.lieq a2, a1, a0, 11
747-
; RV32IXQCI-NEXT: mv a0, a2
733+
; RV32IXQCI-NEXT: qc.selectine a0, a1, a2, 11
748734
; RV32IXQCI-NEXT: ret
749735
entry:
750736
%cmp = icmp ne i32 %b, %a

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