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Implement the alignment parameter in cg_clif
1 parent 0b3f937 commit 108ca9d

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2 files changed

+21
-3
lines changed

2 files changed

+21
-3
lines changed

compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,9 @@ mod simd;
1919

2020
use cranelift_codegen::ir::AtomicRmwOp;
2121
use rustc_middle::ty;
22-
use rustc_middle::ty::GenericArgsRef;
2322
use rustc_middle::ty::layout::ValidityRequirement;
2423
use rustc_middle::ty::print::{with_no_trimmed_paths, with_no_visible_paths};
24+
use rustc_middle::ty::{GenericArgsRef, SimdAlign};
2525
use rustc_span::source_map::Spanned;
2626
use rustc_span::{Symbol, sym};
2727

compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -960,6 +960,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
960960
let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
961961
let ptr_val = ptr.load_scalar(fx);
962962

963+
let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
964+
.unwrap_leaf()
965+
.to_simd_alignment();
966+
967+
let memflags = match alignment {
968+
SimdAlign::Unaligned => MemFlags::new().with_notrap(),
969+
_ => MemFlags::trusted(),
970+
};
971+
963972
for lane_idx in 0..val_lane_count {
964973
let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
965974
let mask_lane = mask.value_lane(fx, lane_idx).load_scalar(fx);
@@ -972,7 +981,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
972981

973982
fx.bcx.switch_to_block(if_enabled);
974983
let offset = lane_idx as i32 * lane_clif_ty.bytes() as i32;
975-
fx.bcx.ins().store(MemFlags::trusted(), val_lane, ptr_val, Offset32::new(offset));
984+
fx.bcx.ins().store(memflags, val_lane, ptr_val, Offset32::new(offset));
976985
fx.bcx.ins().jump(next, &[]);
977986

978987
fx.bcx.seal_block(next);
@@ -996,6 +1005,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
9961005
let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
9971006
let ret_lane_layout = fx.layout_of(ret_lane_ty);
9981007

1008+
let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
1009+
.unwrap_leaf()
1010+
.to_simd_alignment();
1011+
1012+
let memflags = match alignment {
1013+
SimdAlign::Unaligned => MemFlags::new().with_notrap(),
1014+
_ => MemFlags::trusted(),
1015+
};
1016+
9991017
for lane_idx in 0..ptr_lane_count {
10001018
let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
10011019
let ptr_lane = ptr.value_lane(fx, lane_idx).load_scalar(fx);
@@ -1011,7 +1029,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
10111029
fx.bcx.seal_block(if_disabled);
10121030

10131031
fx.bcx.switch_to_block(if_enabled);
1014-
let res = fx.bcx.ins().load(lane_clif_ty, MemFlags::trusted(), ptr_lane, 0);
1032+
let res = fx.bcx.ins().load(lane_clif_ty, memflags, ptr_lane, 0);
10151033
fx.bcx.ins().jump(next, &[res.into()]);
10161034

10171035
fx.bcx.switch_to_block(if_disabled);

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