AMDGPU/GlobalISel: Define instruction mapping for G_INSERT

Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49625 llvm-svn: 339491

Author: tstellar

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

@@ -193,6 +193,8 @@ bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
+ if (!MI.getOperand(i).isReg())
+ continue;
  unsigned Reg = MI.getOperand(i).getReg();
  const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
  if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID)
@@ -331,6 +333,18 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
  OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
  break;
  }
+ case AMDGPU::G_INSERT: {
+ unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
+ AMDGPU::VGPRRegBankID;
+ unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
+ unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
+ unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
+ OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
+ OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
+ OpdsMapping[2] = AMDGPU::getValueMapping(BankID, EltSize);
+ OpdsMapping[3] = nullptr;
+ break;
+ }
  case AMDGPU::G_EXTRACT: {
  unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
  unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir

@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: insert_lo32_i64_ss
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_ss
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_sv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_sv
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_vs
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_vs
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_vv
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_vv
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i96_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
+ ; CHECK-LABEL: name: insert_lo32_i96_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(s32) = COPY $vgpr3
+ %2:_(s96) = G_INSERT %0, %1, 0
+...