Revert "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"

This reverts commit r351125. I missed test changes in an SLPVectorizer test, due to the cost model changes. Reverting for now. llvm-svn: 351129

Author: nikic

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -141,7 +141,6 @@ class VectorLegalizer {
  SDValue ExpandFunnelShift(SDValue Op);
  SDValue ExpandROT(SDValue Op);
  SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
- SDValue ExpandAddSubSat(SDValue Op);
  SDValue ExpandStrictFPOp(SDValue Op);
 
  /// Implements vector promotion.
@@ -778,11 +777,6 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
  case ISD::FMINNUM:
  case ISD::FMAXNUM:
  return ExpandFMINNUM_FMAXNUM(Op);
- case ISD::USUBSAT:
- case ISD::SSUBSAT:
- case ISD::UADDSAT:
- case ISD::SADDSAT:
- return ExpandAddSubSat(Op);
  case ISD::STRICT_FADD:
  case ISD::STRICT_FSUB:
  case ISD::STRICT_FMUL:
@@ -1212,12 +1206,6 @@ SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
  return DAG.UnrollVectorOp(Op.getNode());
 }
 
-SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) {
- if (SDValue Expanded = TLI.expandAddSubSat(Op.getNode(), DAG))
- return Expanded;
- return DAG.UnrollVectorOp(Op.getNode());
-}
-
 SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
  EVT VT = Op.getValueType();
  EVT EltVT = VT.getVectorElementType();

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -5277,22 +5277,6 @@ SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
 
 SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
  unsigned Opcode = Node->getOpcode();
- SDValue LHS = Node->getOperand(0);
- SDValue RHS = Node->getOperand(1);
- EVT VT = LHS.getValueType();
- SDLoc dl(Node);
-
- // usub.sat(a, b) -> umax(a, b) - b
- if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
- SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
- return DAG.getNode(ISD::SUB, dl, VT, Max, RHS);
- }
-
- if (VT.isVector()) {
- // TODO: Consider not scalarizing here.
- return SDValue();
- }
-
  unsigned OverflowOp;
  switch (Opcode) {
  case ISD::SADDSAT:
@@ -5311,7 +5295,11 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
  llvm_unreachable("Expected method to receive signed or unsigned saturation "
  "addition or subtraction node.");
  }
+ assert(Node->getNumOperands() == 2 && "Expected node to have 2 operands.");
 
+ SDLoc dl(Node);
+ SDValue LHS = Node->getOperand(0);
+ SDValue RHS = Node->getOperand(1);
  assert(LHS.getValueType().isScalarInteger() &&
  "Expected operands to be integers. Vector of int arguments should "
  "already be unrolled.");

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

@@ -1780,10 +1780,6 @@ int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
  { ISD::CTPOP, MVT::v16i32, 24 },
  { ISD::CTTZ, MVT::v8i64, 20 },
  { ISD::CTTZ, MVT::v16i32, 28 },
- { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd
- { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq
- { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq
- { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq
  };
  static const CostTblEntry XOPCostTbl[] = {
  { ISD::BITREVERSE, MVT::v4i64, 4 },
@@ -1827,7 +1823,6 @@ int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
  { ISD::UADDSAT, MVT::v32i8, 1 },
  { ISD::USUBSAT, MVT::v16i16, 1 },
  { ISD::USUBSAT, MVT::v32i8, 1 },
- { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd
  { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
  { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
@@ -1863,7 +1858,6 @@ int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
  { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
  { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
  { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
- { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert
  { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
  { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
  { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
@@ -1884,7 +1878,6 @@ int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
  { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
  };
  static const CostTblEntry SSE42CostTbl[] = {
- { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd
  { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
  { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/
  };