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AMDGPU/GlobalISel: Implement select for G_INSERT
Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53116 llvm-svn: 344310
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‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -178,6 +178,34 @@ bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(3).getImm() / 32);
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DebugLoc DL = I.getDebugLoc();
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MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG))
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.addDef(I.getOperand(0).getReg())
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.addReg(I.getOperand(1).getReg())
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.addReg(I.getOperand(2).getReg())
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.addImm(SubReg);
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for (const MachineOperand &MO : Ins->operands()) {
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if (!MO.isReg())
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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continue;
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const TargetRegisterClass *RC =
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TRI.getConstrainedRegClassForOperand(MO, MRI);
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if (!RC)
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continue;
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RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
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}
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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unsigned IntrinsicID = I.getOperand(1).getIntrinsicID();
@@ -640,6 +668,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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return selectG_GEP(I);
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case TargetOpcode::G_IMPLICIT_DEF:
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return selectG_IMPLICIT_DEF(I);
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case TargetOpcode::G_INSERT:
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return selectG_INSERT(I);
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case TargetOpcode::G_INTRINSIC:
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return selectG_INTRINSIC(I, CoverageInfo);
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case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ class AMDGPUInstructionSelector : public InstructionSelector {
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bool selectG_ADD(MachineInstr &I) const;
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bool selectG_GEP(MachineInstr &I) const;
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bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
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bool selectG_INSERT(MachineInstr &I) const;
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bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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---
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name: insert512
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legalized: true
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regBankSelected: true
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# CHECK-LABEL: insert512
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# CHECK: [[BASE:%[0-9]+]]:sreg_512 = IMPLICIT_DEF
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# CHECK: [[VAL:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
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# CHECK: [[BASE0:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE]], [[VAL]], %subreg.sub0
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# CHECK: [[BASE1:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE0]], [[VAL]], %subreg.sub1
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# CHECK: [[BASE2:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE1]], [[VAL]], %subreg.sub2
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# CHECK: [[BASE3:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE2]], [[VAL]], %subreg.sub3
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# CHECK: [[BASE4:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE3]], [[VAL]], %subreg.sub4
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# CHECK: [[BASE5:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE4]], [[VAL]], %subreg.sub5
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# CHECK: [[BASE6:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE5]], [[VAL]], %subreg.sub6
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# CHECK: [[BASE7:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE6]], [[VAL]], %subreg.sub7
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# CHECK: [[BASE8:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE7]], [[VAL]], %subreg.sub8
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# CHECK: [[BASE9:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE8]], [[VAL]], %subreg.sub9
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# CHECK: [[BASE10:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE9]], [[VAL]], %subreg.sub10
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# CHECK: [[BASE11:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE10]], [[VAL]], %subreg.sub11
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# CHECK: [[BASE12:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE11]], [[VAL]], %subreg.sub12
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# CHECK: [[BASE13:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE12]], [[VAL]], %subreg.sub13
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# CHECK: [[BASE14:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE13]], [[VAL]], %subreg.sub14
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# CHECK: [[BASE15:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[BASE14]], [[VAL]], %subreg.sub15
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body: |
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bb.0:
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%0:sgpr(s512) = G_IMPLICIT_DEF
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%1:sgpr(s32) = G_IMPLICIT_DEF
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%2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0
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%3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32
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%4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64
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%5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96
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%6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128
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%7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160
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%8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192
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%9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224
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%10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256
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%11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288
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%12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320
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%13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352
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%14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384
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%15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416
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%16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448
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%17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
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$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
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SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15

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