AMDGPU: Raise the priority of MAD24 in instruction selection.

Summary: We have seen performance regression when v_add3 is generated. The major reason is that the v_mad pattern is broken when v_add3 is generated. We also see the register pressure increased. While we could not properly estimate register pressure during instruction selection, we can give mad a higher priority. In this work, we raise the priority for mad24 in selection and resolve the performance regression. Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D56745 llvm-svn: 351273

Author: Changpeng Fang

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

@@ -842,6 +842,7 @@ def cvt_flr_i32_f32 : PatFrag <
  [{ (void)N; return TM.Options.NoNaNsFPMath; }]
 >;
 
+let AddedComplexity = 2 in {
 class IMad24Pat<Instruction Inst, bit HasClamp = 0> : AMDGPUPat <
  (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
  !if(HasClamp, (Inst $src0, $src1, $src2, (i1 0)),
@@ -853,6 +854,7 @@ class UMad24Pat<Instruction Inst, bit HasClamp = 0> : AMDGPUPat <
  !if(HasClamp, (Inst $src0, $src1, $src2, (i1 0)),
  (Inst $src0, $src1, $src2))
 >;
+} // AddedComplexity.
 
 class RcpPat<Instruction RcpInst, ValueType vt> : AMDGPUPat <
  (fdiv FP_ONE, vt:$src),

llvm/test/CodeGen/AMDGPU/add3.ll

@@ -23,6 +23,32 @@ define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
  ret float %bc
 }
 
+; V_MAD_U32_U24 is given higher priority.
+define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+; GFX9-LABEL: mad_no_add3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4
+; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0
+; GFX9-NEXT: ; return to shader part epilog
+ %a0 = shl i32 %a, 8
+ %a1 = lshr i32 %a0, 8
+ %b0 = shl i32 %b, 8
+ %b1 = lshr i32 %b0, 8
+ %mul1 = mul i32 %a1, %b1
+
+ %c0 = shl i32 %c, 8
+ %c1 = lshr i32 %c0, 8
+ %d0 = shl i32 %d, 8
+ %d1 = lshr i32 %d0, 8
+ %mul2 = mul i32 %c1, %d1
+
+ %add0 = add i32 %e, %mul1
+ %add1 = add i32 %mul2, %add0
+
+ %bc = bitcast i32 %add1 to float
+ ret float %bc
+}
+
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
 ; TODO: with reassociation it is possible to replace a v_add_u32_e32 with a s_add_i32
 define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {