Merge pull request #175 from p12tic/fixes

Miscellaneous fixes

Author: p12tic

simdpp/detail/insn/align.h

@@ -83,7 +83,7 @@ uint8<64> i_align16(const uint8<64>& lower, const uint8<64>& upper)
 template<unsigned shift, unsigned N> SIMDPP_INL
 uint8<N> i_align16(const uint8<N>& lower, const uint8<N>& upper)
 {
- SIMDPP_VEC_ARRAY_IMPL2(uint8<N>, i_align16<shift>, lower, upper);
+ SIMDPP_VEC_ARRAY_IMPL2(uint8<N>, uint8<N>, i_align16<shift>, lower, upper);
 }
 
 // -----------------------------------------------------------------------------
@@ -126,7 +126,7 @@ uint16<32> i_align8(const uint16<32>& lower, const uint16<32>& upper)
 template<unsigned shift, unsigned N> SIMDPP_INL
 uint16<N> i_align8(const uint16<N>& lower, const uint16<N>& upper)
 {
- SIMDPP_VEC_ARRAY_IMPL2(uint16<N>, i_align8<shift>, lower, upper);
+ SIMDPP_VEC_ARRAY_IMPL2(uint16<N>, uint16<N>, i_align8<shift>, lower, upper);
 }
 
 // -----------------------------------------------------------------------------
@@ -203,7 +203,7 @@ uint32<16> i_align4(const uint32<16>& lower, const uint32<16>& upper)
 template<unsigned shift, unsigned N> SIMDPP_INL
 uint32<N> i_align4(const uint32<N>& lower, const uint32<N>& upper)
 {
- SIMDPP_VEC_ARRAY_IMPL2(uint32<N>, i_align4<shift>, lower, upper);
+ SIMDPP_VEC_ARRAY_IMPL2(uint32<N>, uint32<N>, i_align4<shift>, lower, upper);
 }
 
 // -----------------------------------------------------------------------------
@@ -269,7 +269,7 @@ uint64<8> i_align2(const uint64<8>& lower, const uint64<8>& upper)
 template<unsigned shift, unsigned N> SIMDPP_INL
 uint64<N> i_align2(const uint64<N>& lower, const uint64<N>& upper)
 {
- SIMDPP_VEC_ARRAY_IMPL2(uint64<N>, i_align2<shift>, lower, upper);
+ SIMDPP_VEC_ARRAY_IMPL2(uint64<N>, uint64<N>, i_align2<shift>, lower, upper);
 }
 
 // -----------------------------------------------------------------------------
@@ -365,7 +365,7 @@ float32<16> i_align4(const float32<16>& lower, const float32<16>& upper)
 template<unsigned shift, unsigned N> SIMDPP_INL
 float32<N> i_align4(const float32<N>& lower, const float32<N>& upper)
 {
- SIMDPP_VEC_ARRAY_IMPL2(float32<N>, i_align4<shift>, lower, upper);
+ SIMDPP_VEC_ARRAY_IMPL2(float32<N>, float32<N>, i_align4<shift>, lower, upper);
 }
 
 // -----------------------------------------------------------------------------
@@ -439,7 +439,7 @@ float64<8> i_align2(const float64<8>& lower, const float64<8>& upper)
 template<unsigned shift, unsigned N> SIMDPP_INL
 float64<N> i_align2(const float64<N>& lower, const float64<N>& upper)
 {
- SIMDPP_VEC_ARRAY_IMPL2(float64<N>, i_align2<shift>, lower, upper);
+ SIMDPP_VEC_ARRAY_IMPL2(float64<N>, float64<N>, i_align2<shift>, lower, upper);
 }
 
 } // namespace insn

simdpp/detail/insn/bit_and.h

@@ -617,7 +617,7 @@ mask_float64<8> i_bit_and(const mask_float64<8>& a, const mask_float64<8>& b)
 template<class V, class VM> SIMDPP_INL
 V i_bit_and(const V& a, const VM& b)
 {
- SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_and, a, b)
+ SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_and, a, b)
 }
 
 } // namespace insn

simdpp/detail/insn/bit_andnot.h

@@ -617,7 +617,7 @@ mask_float64<8> i_bit_andnot(const mask_float64<8>& a, const mask_float64<8>& b)
 template<class V, class VM> SIMDPP_INL
 V i_bit_andnot(const V& a, const VM& b)
 {
- SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_andnot, a, b)
+ SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_andnot, a, b)
 }
 
 } // namespace insn

simdpp/detail/insn/bit_not.h

@@ -351,7 +351,7 @@ mask_float64<8> i_bit_not(const mask_float64<8>& a)
 template<class V> SIMDPP_INL
 V i_bit_not(const V& a)
 {
- SIMDPP_VEC_ARRAY_IMPL1(V, i_bit_not, a)
+ SIMDPP_VEC_ARRAY_IMPL1(V, V, i_bit_not, a)
 }
 
 } // namespace insn

simdpp/detail/insn/bit_or.h

@@ -415,7 +415,7 @@ mask_float64<8> i_bit_or(const mask_float64<8>& a, const mask_float64<8>& b)
 template<class V, class VM> SIMDPP_INL
 V i_bit_or(const V& a, const VM& b)
 {
- SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_or, a, b)
+ SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_or, a, b)
 }
 
 } // namespace insn

simdpp/detail/insn/bit_select.h

@@ -697,7 +697,7 @@ static SIMDPP_INL
 template<class V1, class V2, class V3> SIMDPP_INL
  V1 i_bit_select(const V1& on, const V2& off, const V3& mask)
 {
- SIMDPP_VEC_ARRAY_IMPL3(V1, i_bit_select, on, off, mask)
+ SIMDPP_VEC_ARRAY_IMPL3(V1, V1, i_bit_select, on, off, mask)
 }
 
 

simdpp/detail/insn/bit_xor.h

@@ -418,7 +418,7 @@ mask_float64<8> i_bit_xor(const mask_float64<8>& a, const mask_float64<8>& b)
 template<class V, class VM> SIMDPP_INL
 V i_bit_xor(const V& a, const VM& b)
 {
- SIMDPP_VEC_ARRAY_IMPL2(V, i_bit_xor, a, b)
+ SIMDPP_VEC_ARRAY_IMPL2(V, V, i_bit_xor, a, b)
 }
 
 } // namespace insn

simdpp/detail/insn/blend.h

@@ -666,7 +666,7 @@ mask_float64<8> i_blend(const mask_float64<8>& on, const mask_float64<8>& off, c
 template<class V1, class V2, class V3> SIMDPP_INL
 V1 i_blend(const V1& on, const V2& off, const V3& mask)
 {
- SIMDPP_VEC_ARRAY_IMPL3(V1, i_blend, on, off, mask)
+ SIMDPP_VEC_ARRAY_IMPL3(V1, V1, i_blend, on, off, mask)
 }
 
 

simdpp/detail/insn/cmp_eq.h

@@ -405,7 +405,7 @@ mask_float64<8> i_cmp_eq(const mask_float64<8>& a, const mask_float64<8>& b)
 template<class V> SIMDPP_INL
 typename V::mask_vector_type i_cmp_eq(const V& a, const V& b)
 {
- SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_eq, a, b);
+ SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_eq, a, b);
 }
 
 } // namespace insn

simdpp/detail/insn/cmp_ge.h

@@ -406,7 +406,7 @@ mask_float64<8> i_cmp_ge(const float64<8>& a, const float64<8>& b)
 template<class V> SIMDPP_INL
 typename V::mask_vector_type i_cmp_ge(const V& a, const V& b)
 {
- SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, i_cmp_ge, a, b);
+ SIMDPP_VEC_ARRAY_IMPL2(typename V::mask_vector_type, V, i_cmp_ge, a, b);
 }
 
 } // namespace insn