[AArch64][GlobalISel] SIMD fpcvt codegen for fptoi(_sat) (llvm#160831)

This is followup patch to llvm#157680, which allows simd fpcvt instructions to be generated from fptoi(_sat) nodes.

Author: Lukacma

llvm/lib/Target/AArch64/AArch64InstrFormats.td

@@ -5298,7 +5298,7 @@ multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
 }
 
 multiclass FPToIntegerSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, 
- SDPatternOperator OpN = null_frag> {
+ SDPatternOperator OpN> {
  // double-precision to 32-bit SIMD/FPR
  def SDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, FPR32, asm,
  [(set FPR32:$Rd, (i32 (OpN (f64 FPR64:$Rn))))]> {

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -856,19 +856,29 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
  break;
  }
  case TargetOpcode::G_FPTOSI_SAT:
- case TargetOpcode::G_FPTOUI_SAT: {
+ case TargetOpcode::G_FPTOUI_SAT:
+ case TargetOpcode::G_FPTOSI:
+ case TargetOpcode::G_FPTOUI: {
  LLT DstType = MRI.getType(MI.getOperand(0).getReg());
  if (DstType.isVector())
  break;
  if (DstType == LLT::scalar(16)) {
  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
  break;
  }
- OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
+ TypeSize DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
+ TypeSize SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, TRI);
+ if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&
+ all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
+ [&](const MachineInstr &UseMI) {
+ return onlyUsesFP(UseMI, MRI, TRI) ||
+ prefersFPUse(UseMI, MRI, TRI);
+ }))
+ OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
+ else
+ OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
  break;
  }
- case TargetOpcode::G_FPTOSI:
- case TargetOpcode::G_FPTOUI:
  case TargetOpcode::G_INTRINSIC_LRINT:
  case TargetOpcode::G_INTRINSIC_LLRINT:
  if (MRI.getType(MI.getOperand(0).getReg()).isVector())

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

@@ -96,7 +96,7 @@ body: |
  ; CHECK-NEXT: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
  ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
  ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY2]](s32), [[COPY3]], [[SITOFP]]
- ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
+ ; CHECK-NEXT: [[FPTOSI:%[0-9]+]]:fpr(s32) = G_FPTOSI [[SELECT]](s32)
  %0:_(s32) = COPY $w0
  %2:_(s32) = COPY $w1
  %3:_(s32) = COPY $w2